74ACT175

74AC175, 74ACT175 Quad D-Type Flip-Flop April 2007 74AC175, 74ACT175 Quad D-Type Flip-Flop Features ■ ICC reduced by 50% ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Asynchronous common reset ■ True and complement output ■ Outputs source/sink 24mA ■ ACT175 has TTL-compatible inputs tm General Description The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-toHIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW. Ordering Information Order Number 74AC175SC 74AC175SJ 74AC175MTC 74AC175PC 74ACT175SC 74ACT175SJ 74ACT175MTC Package Number M16A M16D MTC16 N16E M16A M16D MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin Descriptions Pin Names D0–D3 CP MR Q0–Q3 Q0–Q3 Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs FACT™ is a trademark of Fairchild Semiconductor Corporation. ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 74AC175, 74ACT175 Quad D-Type Flip-Flop Logic Symbol Functional Description The AC/ACT175 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flipflops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The AC/ ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Truth Table IEEE/IEC Inputs @ tn, MR = H Dn L H H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Outputs @ tn+1 Qn L H Qn H L Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 2 74AC175, 74ACT175 Quad D-Type Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Supply Voltage DC Input Diode Current VI = –0.5V VI = VCC + 0.5V VI IOK DC Input Voltage DC Output Diode Current VO = –0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage Parameter Rating –0.5V to +7.0V –20mA +20mA –0.5V to VCC + 0.5V –20mA +20mA –0.5V to VCC + 0.5V ±50mA ±50mA –65°C to +150°C 140°C DC Output Source or Sink Current Storage Temperature Junction Temperature ICC or IGND DC VCC or Ground Current per Output Pin Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Supply Voltage AC ACT VI VO TA ∆V / ∆t ∆V / ∆t Input Voltage Output Voltage Operating Temperature Parameter Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC –40°C to +85°C 125mV/ns 125mV/ns Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 3 74AC175, 74ACT175 Quad D-Type Flip-Flop DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA TA = –40°C to +85°C Guaranteed Limits Units V 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 –75 µA mA mA µA V V V Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIL or VIH: 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 VIN = VIL or VIH: 3.0 4.5 5.5 IIN(3) IOLD IOHD ICC (3) IOH = –12mA IOH = –24mA IOH = –24mA(1) IOUT = 50µA IOL = 12mA IOL = 24mA IOL = 24mA(1) VI = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND Maximum Input Leakage Current Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 40.0 Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 4 74AC175, 74ACT175 Quad D-Type Flip-Flop DC Electrical Characteristics for ACT Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA VIN = VIL or VIH: TA = –40°C to +85°C Guaranteed Limits Units V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 1.5 75 –75 µA mA mA mA µA V Typ. 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 ±0.1 0.6 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 IOH = –24mA IOH = –24mA(4) IOUT = 50µA VIN = VIL or VIH: 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(5) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 IOL= 24mA IOL= 24mA(4) VI = VCC, GND VI = VCC – 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 4.0 40.0 Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 5 74AC175, 74ACT175 Quad D-Type Flip-Flop AC Electrical Characteristics for AC TA = +25°C, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL TA = –40°C to +85°C, CL = 50pF Min. 139 187 12.0 9.0 13.0 9.5 12.5 9.0 11.0 8.5 2.0 1.0 2.0 1.5 2.5 1.5 2.5 1.5 13.5 9.5 14.5 10.5 13.5 10.0 12.5 9.0 ns ns ns ns Parameter Maximum Clock Frequency Propagation Delay, CP to Qn or Qn Propagation Delay, CP to Qn or Qn Propagation Delay, MR to Qn Propagation Delay, MR to Qn VCC (V)(6) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min. 149 187 2.0 1.5 2.5 1.5 3.0 2.0 3.0 2.0 Typ. 214 244 9.5 7.0 8.5 6.0 7.5 5.5 8.5 6.0 Max. Max. Units MHz Note: 6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. AC Operating Requirements for AC TA = +25°C, CL = 50pF Symbol tS tH tW tW tREC TA = –40°C to +85°C, CL = 50pF Units ns ns ns ns ns 4.5 3.0 1.0 1.0 4.5 3.5 5.0 3.5 0 0 Parameter Setup Time, HIGH or LOW, Dn to CP Hold Time, HIGH or LOW, Dn to CP CP Pulse Width, HIGH or LOW MR Pulse Width, LOW Recovery Time, MR to CP VCC (V)(7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Typ. 2.0 1.0 1.0 1.0 2.5 2.0 2.5 2.0 –2.0 –1.0 Guaranteed Minimum 4.5 3.0 1.0 1.0 4.5 3.5 4.5 3.5 0 0 Note: 7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 6 74AC175, 74ACT175 Quad D-Type Flip-Flop AC Electrical Characteristics for ACT TA = +25°C, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL TA = –40°C to +85°C, CL = 50pF Min. 145 10.0 11.0 9.5 9.5 1.5 1.5 1.5 1.5 11.0 12.0 10.5 10.5 Parameter Maximum Clock Frequency Propagation Delay, CP to Qn or Qn Propagation Delay, CP to Qn or Qn Propagation Delay, MR to Qn Propagation Delay, MR to Qn VCC (V)(8) 5.0 5.0 5.0 5.0 5.0 Min. 175 2.0 2.0 2.0 2.0 Typ. 236 6.0 7.0 6.0 5.5 Max. Max. Units MHz ns ns ns ns Note: 8. Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements for ACT TA = +25°C, CL = 50pF Symbol tS (H) tS (L) tH tW tW trec Hold Time, HIGH or LOW, Dn to CP CP Pulse Width,HIGH or LOW MR Pulse Width, LOW Recovery Time, MR to CP 5.0 5.0 5.0 5.0 TA = –40°C to +85°C, CL = 50pF Units ns ns ns ns ns 2.0 2.5 1.0 3.5 4.0 0 Parameter Setup Time, Dn to CP VCC (V)(9) 5.0 Typ. 3.0 3.0 0 4.0 4.0 0 Guaranteed Minimum 2.0 2.5 1.0 3.0 3.0 0 Note: 9. Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Conditions VCC = OPEN VCC = 5.0V Typ. 4.5 45.0 Units pF pF ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 7 74AC175, 74ACT175 Quad D-Type Flip-Flop Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 8 74AC175, 74ACT175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 9 74AC175, 74ACT175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 4. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 10 74AC175, 74ACT175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 5. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 11 74AC175, 74ACT175 Quad D-Type Flip-Flop TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Rev. 1.4 www.fairchildsemi.com 12