74ACT245SC

74AC245 • 74ACT245 Octal Bidirectional Transceiver with 3-STATE November 1988 Revised March 2005 74AC245 • 74ACT245 Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs General Description The AC/ACT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 24 mA at both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active-HIGH) enables data from A ports to B ports; Receive (active-LOW) enables data from B ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition. Features s ICC and IOZ reduced by 50% s Non-inverting buffers s Bidirectional data path s A and B outputs source/sink 24 mA s ACT245 has TTL-compatible inputs Ordering Code: Order Number 74AC245SC 74AC245SJ 74AC245MTC 74AC245PC 74ACT245SC 74ACT245SCX_NL (Note 1) 74ACT245SJ 74ACT245MSA 74ACT245MTC 74ACT245MTCX_NL (Note 1) 74ACT245PC Package Number M20B M20D MTC20 N20A M20B M20B M20D MSA20 MTC20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. FACT¥ is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS009944 www.fairchildsemi.com 74AC245 • 74ACT245 Connection Diagram Pin Descriptions Pin Description Names OE T/R A0–A7 B0–B7 Output Enable Input Transmit/Receive Input Side A 3-STATE Inputs or 3-STATE Outputs Side B 3-STATE Inputs or 3-STATE Outputs Truth Table Inputs Logic Symbols Outputs OE L L H H H IGH Voltage Level L LOW Voltage Level X Immaterial T/R L H X Bus B Data to Bus A Bus A Data to Bus B HIGH-Z State IEEE/IEC www.fairchildsemi.com 2 74AC245 • 74ACT245 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI 0.5V to 7.0V 20 mA 20 mA 0.5V to VCC  0.5V 20 mA 20 mA 0.5V to VCC  0.5V r50 mA r50 mA 65qC to 150qC 140qC Recommended Operating Conditions Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT¥ circuits outside databook specifications. 0.5V VCC  0.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO 0.5V VCC  0.5V 40qC to 85qC DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 125 mV/ns DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD IOZT Maximum Input Leakage Current Dynamic Output Current Minimum (Note 4) Maximum I/O Leakage Current 5.5 5.5 5.5 5.5 5.5 4.0 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 25qC TA 40qC to 85qC 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 Guaranteed Limits Units VOUT V Conditions 0.1V or VCC  0.1V VOUT 0.1V V or VCC  0.1V V IOUT VIN 50 PA VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 V V IOH IOH IOH IOUT VIN 12 mA 24 mA 24 mA (Note 3) 50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 3) VCC, GND 1.65V Max 3.85V Min VCC or GND VIL, VIH VCC, GND VCC, GND 0.44 0.44 0.44 V IOL IOL IOL VI r 0.1 r 1.0 75 PA mA mA VOLD VOHD VIN VI VO VI (OE) 75 40.0 ICC (Note 5) Maximum Quiescent Supply Current PA PA r 0.3 r 3.0 Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: M aximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC245 • 74ACT245 DC Characteristics for ACT Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC IOZT Maximum Input Leakage Current Maximum ICC/Input Dynamic Output Current Minimum (Note 7) Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 5.5 5.5 5.5 5.5 4.0 0.6 1.5 75 mA mA mA VI VCC  2.1V 1.65V Max 3.85V Min VCC V IL, VIH 5.5 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 25qC TA 40qC to 85qC 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 Guaranteed Limits Units V V V VOUT VOUT IOUT VIN IOH V V IOH IOUT VIN V IOL IOL VI Conditions 0.1V 0.1V or VCC  0.1V or VCC  0.1V 50 PA VIL or VIH 24 mA 24 mA (Note 6) 50 PA VIL or VIH 24 mA 24 mA (Note 6) VCC, GND r0.1 r1.0 PA VOLD VOHD VIN or GND VI (OE) VI VO 75 40.0 PA r0.3 r3.0 PA VCC, GND VCC, GND Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC VCC Symbol Parameter (V) (Note 8) tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay An to Bn or Bn to An Propagation Delay An to Bn or Bn to An Output Enable Time Output Enable Time Output Disable Time Output Disable Time 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Note 8: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V TA CL Min 1.5 1.5 1.5 1.5 2.5 1.5 2.5 1.5 2.0 1.5 2.0 1.5 25qC 50 pF Typ 5.0 3.5 5.0 3.5 7.0 5.0 7.5 5.5 6.5 5.5 7.0 5.5 Max 8.5 6.5 8.5 6.0 11.5 8.5 12.0 9.0 12.0 9.0 11.5 9.0 TA 40qC to 85qC CL 50 pF Max 9.0 7.0 9.0 7.0 12.5 9.0 13.5 9.5 12.5 10.0 13.0 10.0 ns ns ns ns ns ns Units Min 1.0 1.0 1.0 1.0 2.0 1.0 2.0 1.0 1.0 1.0 1.5 1.0 www.fairchildsemi.com 4 74AC245 • 74ACT245 AC Electrical Characteristics for ACT VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to Bn or Bn to An Propagation Delay An to Bn or Bn to An Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 1.5 1.5 1.5 2.0 5.0 5.5 5.5 5.0 10.0 10.0 10.0 10.0 1.5 1.5 1.0 1.5 11.0 12.0 11.0 11.0 ns ns ns ns 5.0 1.5 4.0 8.0 1.0 9.0 ns (V) (Note 9) 5.0 Min 1.5 TA CL 25qC 50 pF Typ 4.0 Max 7.5 TA 40qC to 85qC CL 50 pF Max 8.0 ns Units Min 1.5 Note 9: Voltage Range 5.0 is 5.0V r 0.5V Capacitance Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Typ 4.5 15.0 45.0 Units pF pF pF VCC VCC VCC OPEN 5.0V 5.0V Conditions 5 www.fairchildsemi.com 74AC245 • 74ACT245 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74AC245 • 74ACT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74AC245 • 74ACT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 8 74AC245 • 74ACT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com 74AC245 • 74ACT245 Octal Bidirectional Transceiver with 3-STATE Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com