74ACT2708

74ACT2708 64 x 9 First-In, First-Out Memory February 1989 Revised January 1999 74ACT2708 64 x 9 First-In, First-Out Memory General Description The ACT2708 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data rate makes it ideal for high-speed applications. It uses a dual port RAM architecture with pointer logic to achieve the high speed with negligible fallthrough time. Separate Shift-In (SI) and Shift-Out (SO) clocks control the use of synchronous or asynchronous write or read. Other controls include a Master Reset (MR) and Output Enable (OE) for initializing the internal registers and allowing the data outputs to be 3-STATE. Input Ready (IR) and Output Ready (OR) signal when the FIFO is ready for I/O operations. The status flags HF and FULL indicate when the FIFO is full, empty or half full. The FIFO can be expanded to provide different word lengths by tying off unused data inputs. Features s 64-words by 9-bit dual port RAM organization s 85 MHz shift-in, 60 MHz shift-out data rate, typical s Expandable in word width only s TTL-compatible inputs s Asynchronous or synchronous operation s Asynchronous master reset s Outputs source/sink 8 mA s 3-STATE outputs s Full ESD protection s Input and output pins directly in line for easy board layout s TRW 1030 work-alike operation Applications • High-speed disk or tape controllers • A/D output buffers • High-speed graphics pixel buffer • Video time base correction • Digital filtering Ordering Code: Order Number 74ACT2708PC Package Number N28B Package Description 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for DIP Pin Descriptions Pin Names D0–D8 MR OE SI SO IR OR HF FULL O0–O8 Description Data Inputs Master Reset Output Enable Input Shift-In Shift-Out Input Ready Output Ready Half Full Flag Full Flag Data Outputs FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010144.prf www.fairchildsemi.com 74ACT2708 Logic Symbol Block Diagram www.fairchildsemi.com 2 74ACT2708 Functional Description INPUTS Data Inputs (D0–D8) Data inputs for 9-bit wide data are TTL-compatible. Word width can be reduced by trying unused inputs to ground and leaving the corresponding outputs open. Reset (MR) Reset is accomplished by pulsing the MR input LOW. During normal operation MR is HIGH. A reset is required after power up to guarantee correct operation. On reset, the data outputs go LOW, IR goes HIGH, OR goes LOW, FH and FULL go LOW. During reset, both internal read and write pointers are set to the first location in the array. Shift-In (SI) Data is written into the FIFO by pulsing SI HIGH. When Shift-In goes HIGH, the data is loaded into an internal data latch. Data setup and hold times need to be adhered to with respect to the falling edge of SI. The write cycle is complete after the falling edge of SI. The shift-in is independent of any ongoing shift-out operation. After the first word has been written into the FIFO, the falling edge of SI makes HF go HIGH, indicating a non-empty FIFO. The first data word appears at the output after the falling edge of SI. After half the memory is filled, the next rising edge of SI makes FULL go HIGH indicating a half-full FIFO. When the FIFO is full, any further shift-ins are disabled. When the FIFO is empty and OE is LOW, the falling edge of the first SI will cause the first data word just shifted-in to appear at the output, even though SO may be LOW. Shift-Out (SO) Data is read from the FIFO by the Shift-Out signal provided the FIFO is not empty. SO going HIGH causes OR to go LOW indicating that output stage is busy. On the falling edge of SO, new data reaches the output after propagation delay tD. If the last data has been shifted-out of the memory, OR continues to remain LOW, and the last word shifted-out remains on the output pins. Output Enable (OE) OE LOW enables the 3-STATE output buffers. When OE is HIGH, the outputs are in a 3-STATE mode. Inputs MR H L SI X X SO X X IR X H OR X L Half-Full (HF) This status flag along with the FULL status flag indicates the degree of fullness of the FIFO. On reset, HF is LOW; it rises on the falling edge of the first SI. The rising edge of the SI pulse that fills up the FIFO makes HF go LOW. Going from the empty to the full state with SO LOW, the falling edge of the first SI causes HF to go HIGH, the rising edge of the 33rd SI causes FULL to go HIGH, and the rising edge of the 64th SI causes HF to go LOW. When the FIFO is full, HF is LOW and the falling edge of the first shift-out causes HF to go HIGH indicating a “nonfull” FIFO. Full Flag (FULL) This status flag along with the HF status flag indicates the degree of fullness of the FIFO. On reset, FULL is LOW. When half the memory is filled, on the rising edge of the next SI, the FULL flag goes HIGH. It remains set until the difference between the write pointer and the read pointer is less than or equal to one-half of the total memory of the device. The FULL flag then goes LOW on the rising edge of the next SO. Status Flags Truth Table HF L L H H FULL L H L H Full HF tPHL Propagation Delay, tIF SI to Full Condition tPLH Propagation Delay, tIE SI to Not Empty tPLH Propagation Delay, tIOR SI to OR tPLH Propagation Delay tMRIRH MR to IR tPHL Propagation Delay, tMRORL MR to OR tPHL Propagation Delay, tMRO MR to Full Flag tPHL Propagation Delay, tMRE MR to HF Flag tPHL Propagation Delay, tMRONL MR to On, LOW tPLH Propagation Delay, tD SO to Data Out tPHL Propagation Delay, tD SO to Data Out tPHL Propagation Delay, tOHF SO to < HF tPLH Propagation Delay, tOF SO to Not Full tPLH, tPHL Propagation Delay, tOR SO to OR tPHL Propagation Delay, tOE SO to Empty tPLH Propagation Delay, tOD5 SI to New Data Out tPHL Propagation Delay, tOD5 SI to New Data Out tPLH Propagation Delay, tX1 SI to HF tPLH Fall-Through Time, tFTO SI to OR tW R Pulse Width, tOP 5.0 12.5 17.0 26.0 12.5 30.5 ns 5.0 3.5 13.5 21.0 1.5 24.0 ns 5.0 3.5 10.0 16.0 2.5 18.0 ns 5.0 7.0 19.0 29.5 6.0 34.5 ns 5.0 7.0 19.0 30.5 6.0 35.5 ns 5.0 3.5 9.5 15.5 3.0 17.5 ns 5.0 2.5 7.0 11.5 2.5 13.5 ns 5.0 5.0 12.5 19.5 5.0 22.0 ns 5.0 3.5 8.5 13.5 3.5 15.5 ns 5.0 6.5 18.5 29.5 6.5 34.5 ns 5.0 6.5 18.5 27.0 6.5 31.0 ns 5.0 3.0 9.0 15.0 3.0 17.0 ns 5.0 8.0 17.5 27.5 8.0 30.5 ns 5.0 3.5 9.0 14.0 3.5 16.0 ns 5.0 7.0 16.5 25.5 7.0 29.0 ns 5.0 3.0 8.5 13.5 3.0 15.5 ns 5.0 4.0 13.5 16.5 4.0 19.0 ns 5.0 4.0 10.0 15.5 4.0 17.5 ns 5.0 4.5 10.5 16.5 4.5 19.5 ns 5.0 4.0 10.5 17.0 4.0 19.5 ns 5.0 2.0 6.5 11.0 1.5 12.0 ns 5.0 Min 2.0 TA = +25°C CL = 50 pF Typ 6.5 Max 11.0 TA = −40°C to +85°C CL = 50 pF Min 1.5 Max 12.5 ns Units 11 www.fairchildsemi.com 74ACT2708 AC Electrical Characteristics (Continued) TA = +25°C CL = 50 pF Min 14.5 16.5 17.5 6.0 Typ 20.5 28.0 30.0 15.0 Max 30.5 43.0 46.5 23.5 TA = −40°C to +85°C CL = 50 pF Min 14.5 16.5 17.5 2.5 Max 36.5 51.5 56.0 28.0 ns ns ns ns Units VCC Symbol Parameter (V) (Note 5) tW tW tW tPLH HF Pulse Width, tX3 IR Pulse Width, tIP HF Pulse Width, t3F Fall-Through Times, tFT SO to IR tPZL Output Enable OE to On tPLZ Output Disable OE to On tPZH Output Enable OE to On tPHZ Output Disable OE to On fSI Maximum SI Clock Frequency fSO Maximum SO Clock Frequency Note 5: Voltage Range 5.0 is 5.0V ± 0.5V 5.0 5.0 5.0 5.0 5.0 2.0 6.5 11.0 1.5 12.0 ns 5.0 1.5 5.0 8.5 1.5 9.5 ns 5.0 2.0 7.0 12.0 1.5 13.0 ns 5.0 1.5 7.0 12.0 1.5 13.0 ns 5.0 55 85 45 MHz 5.0 42 60 35 MHz AC Operating Requirements VCC Symbol Parameter (V) (Note 6) tW(H) tW(L) SI Pulse Width, tSIH SI Pulse Width, tSIL 5.0 5.0 TA = +25°C CL = 50 pF Typ 3.5 6.0 6.5 10.0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 7.5 12.0 ns ns Units tS Setup Time, HIGH or LOW, Dn to SI 5.0 1.0 3.5 4.5 ns tH Hold Time, HIGH or LOW, Dn to SI 5.0 1.5 3.5 4.5 ns tW trec MR Pulse Width, tMRW Recovery Time, tMRSIH MR to SI 5.0 5.0 13.0 4.5 20.0 7.5 24.5 8.5 ns ns tW(H) tW(L) SO Pulse Width, tSOH SO Pulse Width, tSOL 5.0 5.0 7.5 9.0 6.5 14.0 8.0 17.0 ns ns Note 6: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 20.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V www.fairchildsemi.com 12 74ACT2708 64 x 9 First-In, First-Out Memory Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Package Number N28B LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.