74ACT534

74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs April 2007 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs Features ■ ICC and IOZ reduced by 50% ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ 3-STATE outputs for bus-oriented applications ■ Outputs source/sink 24mA ■ ACT534 has TTL-compatible inputs ■ Inverted output version of ACT374 tm General Description The ACT534 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The ACT534 is the same as the ACT374 except that the outputs are inverted. Ordering Information Order Number 74ACT534SC 74ACT534SJ Package Number M20B M20D Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names D0–D7 CP OE O0–O7 Data Inputs Clock Pulse Input 3-STATE Output Enable Input Complementary 3-STATE Outputs Description FACT™ is a trademark of Fairchild Semiconductor Corporation. ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs Functional Description The ACT534 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-toHIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table Inputs CP OE L L L X L H Output D H L X X O L H O0 Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Z = High Impedance O0 = Value stored from previous clock cycle Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 2 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Supply Voltage DC Input Diode Current VI = –0.5V VI = VCC + 0.5V VI IOK DC Input Voltage DC Output Diode Current VO = –0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage Parameter Rating –0.5V to +7.0V –20mA +20mA –0.5V to VCC + 0.5V –20mA +20mA –0.5V to VCC + 0.5V ±50mA ±50mA –65°C to +150°C 140°C DC Output Source or Sink Current Storage Temperature Junction Temperature ICC or IGND DC VCC or Ground Current per Output Pin Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA ∆V / ∆t Supply Voltage Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate: Parameter Rating 4.5V to 5.5V 0V to VCC 0V to VCC –40°C to +85°C 125mV/ns VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 3 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA VIN = VIL or VIH: TA = –40°C to +85°C Guaranteed Limits Units V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±2.5 1.5 75 –75 µA µA mA mA mA µA V Typ. 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 ±0.1 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 IOH = –24mA IOH = –24mA(1) IOUT = 50µA VIN = VIL or VIH: 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 IOL = 24mA IOL = 24mA(1) VI = VCC, GND VI = VIL, VIH; VO = VCC, GND VI = VCC – 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 0.6 ±0.25 4.0 40.0 Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 4 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs AC Electrical Characteristics TA = +25°C, CL = 50pF Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ TA = –40°C to +85°C, CL = 50pF Min. 120 2.0 2.0 2.0 2.0 1.0 1.0 Parameter Maximum Clock Frequency Propagation Delay, CP to Qn Propagation Delay, CP to Qn Output Enable Time Output Enable Time Output Disable Time Output Disable Time VCC (V)(3) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Min. 2.5 2.0 2.5 2.0 1.5 1.5 Typ. 100 6.5 6.0 6.5 6.0 7.0 5.5 Max. 11.5 10.5 12.0 11.0 12.5 10.5 Max. 12.5 12.0 12.5 11.5 13.5 10.5 Units MHz ns ns ns ns ns ns Note: 3. Voltage range 5.0 is 5.0V ± 0.5V. AC Operating Requirements TA = +25°C, CL = 50pF Symbol tS tH tW TA = –40°C to +85°C, CL = 50pF Units ns ns ns 4.0 1.5 3.5 Parameter Setup Time, HIGH or LOW, Dn to CP Hold Time, HIGH or LOW, Dn to CP CP Pulse Width, HIGH or LOW VCC (V)(4) 5.0 5.0 5.0 Typ. 1.0 –1.0 2.0 Guaranteed Minimum 3.5 1.0 3.5 Note: 4. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Conditions VCC = OPEN VCC = 5.0V Typ. 4.5 40.0 Units pF pF ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 5 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 2. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 6 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 7 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1988 Fairchild Semiconductor Corporation 74ACT534 Rev. 1.4 www.fairchildsemi.com 8