74ACT573

74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs November 1988 Revised October 1999 74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs General Description The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides. Features s ICC and IOZ reduced by 50% s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74AC373 and 74ACT373 s 3-STATE outputs for bus interfacing s Outputs source/sink 24 mA s 74ACT573 has TTL-compatible inputs Ordering Code: Order Number 74AC573SC 74AC573SJ 74AC573MTC 74AC573PC 74ACT573SC 74ACT573SJ 74ACT573MTC 74ACT573PC Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 LE OE O0–O7 Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009973 www.fairchildsemi.com 74AC573 • 74ACT573 Functional Description The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs OE L L L H H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Outputs D H L X X On H L O0 Z LE H H L X Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74AC573 • 74ACT573 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) (PDIP) 140°C ±50 mA −65°C to +150°C ±50 mA −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V −0.5V to +7.0V Recommended Operating Conditions Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT™ circuits outside databook specifications. 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 3) IOLD IOHD ICC (Note 3) IOZ Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Maximum 3-STATE Leakage Current 5.5 ±0.25 ±2.5 µA 5.5 5.5 5.5 5.5 4.0 0.002 0.001 0.001 TA = +25°C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 TA = −40°C to +85°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 ±1.0 75 −75 40.0 µA mA mA µA V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 4: M aximum test duration 2.0 ms, one output loaded at a time. Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V V IOH = −12 mA IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA 3 www.fairchildsemi.com 74AC573 • 74ACT573 AC Electrical Characteristics for AC VCC Symbol tPHL tPLH tPLH tPHL tPZL tPZH tPHZ tPLZ Note 5: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V TA = +25°C CL = 50 pF Min 0.5 1.5 2.5 2.0 2.5 1.5 1.0 1.0 Typ 8.5 5.5 8.5 6.0 8.5 6.0 9.0 6.0 Max 10.5 7.0 12.0 8.0 13.0 8.5 14.5 9.5 TA = −40°C to +85°C CL = 50 pF Min 2.5 1.5 2.5 2.0 2.5 1.5 1.0 1.0 Max 11.0 7.5 12.5 8.5 13.5 9.0 15.0 10.0 ns ns ns ns Units Parameter Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time (V) (Note 5) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 AC Operating Requirements for AC VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH (V) (Note 6) 3.3 5.0 3.3 5.0 3.3 5.0 Note 6: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V TA = +25°C CL = 50 pF Typ 0 0 0 0 2.0 2.0 3.0 3.0 1.5 1.5 4.0 4.0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 3.0 3.0 1.5 1.5 4.0 4.0 ns ns ns Units www.fairchildsemi.com 4 74AC573 • 74ACT573 DC Electrical Characteristics for ACT Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 8) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 VCC (V) 4.5 5.5 4.5 TA = +25°C Typ 1.5 1.5 1.5 5.5 4.49 5.49 2.0 2.0 0.8 1.5 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 ±0.25 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±2.5 1.5 75 −75 40.0 µA µA mA mA mA µA V Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 7) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 7) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: M aximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for ACT VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Dn to On Propagation Delay LE to On Propagation Delay LE to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 9) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Min 2.5 3.0 2.5 2.0 1.5 2.5 1.5 TA = +25°C CL = 50 pF Typ 6.0 6.0 5.5 5.5 5.5 6.5 5.0 Max 10.5 10.5 9.5 10.0 9.5 11.0 8.5 TA = −40°C to +85°C CL = 50 pF Min 2.0 2.5 2.0 1.5 1.5 1.5 1.0 Max 12.0 12.0 10.5 11.0 10.5 12.5 9.5 ns ns ns ns ns ns ns Units Note 9: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.fairchildsemi.com 74AC573 • 74ACT573 AC Operating Requirements for ACT VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH Note 10: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Typ 1.5 −1.5 2.0 3.0 0 3.5 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 3.5 0 4.0 ns ns ns Units (V) (Note 10) 5.0 5.0 5.0 Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance for AC for ACT Typ 5.0 25.0 42.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions www.fairchildsemi.com 6 74AC573 • 74ACT573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com 74AC573 • 74ACT573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74AC573 • 74ACT573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com 74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com