74ACT573SC

74AC573, 74ACT573 Octal Latch with 3-STATE Outputs March 2007 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Features ■ ICC and IOZ reduced by 50% ■ Inputs and outputs on opposite sides of package tm General Description The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides. allowing easy interface with microprocessors ■ Useful as input or output port for microprocessors ■ Functionally identical to 74AC373 and 74ACT373 ■ 3-STATE outputs for bus interfacing ■ Outputs source/sink 24mA ■ 74ACT573 has TTL-compatible inputs Ordering Information Order Number 74AC573SC 74AC573SJ 74AC573MTC 74ACT573SC 74ACT573SCX_NL(1) 74ACT573SJ 74ACT573MTC 74ACT573PC Package Number M20B M20D MTC20 M20B M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Note: 1. Device available in Tape and Reel only. FACT™ is a trademark of Fairchild Semiconductor Corporation. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Logic Symbols IEEE/IEC Connection Diagram Truth Table Inputs OE L L L H Outputs D H L X X LE H H L X On H L O0 Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Pin Descriptions Pin Names D0–D7 LE OE O0–O7 Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs Functional Description The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 2 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 3 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Supply Voltage DC Input Diode Current VI = –0.5V VI = VCC + 0.5V VI IOK DC Input Voltage DC Output Diode Current VO = –0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage Parameter Rating –0.5V to +7.0V –20mA +20mA –0.5V to VCC + 0.5V –20mA +20mA –0.5V to VCC + 0.5V ±50mA ±50mA –65°C to +150°C 140°C DC Output Source or Sink Current Storage Temperature Junction Temperature ICC or IGND DC VCC or Ground Current per Output Pin Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Supply Voltage AC ACT VI VO TA ∆V / ∆t ∆V / ∆t Input Voltage Output Voltage Operating Temperature Parameter Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC –40°C to +85°C 125mV/ns 125mV/ns Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 4 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs DC Electrical Characteristics for AC TA = +25°C Symbol VIH TA = –40°C to +85°C Units V 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 V 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 –75 µA mA mA µA µA V V V Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 Guaranteed Limits 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIL or VIH: 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 VIN = VIL or VIH: 3.0 4.5 5.5 IIN (3) IOH = –12mA IOH = –24mA IOH = –24mA(2) 0.002 0.001 0.001 IOL = 12mA IOL = 24mA IOL = 24mA(2) VI = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND VI (OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND IOUT = 50µA 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 Maximum Input Leakage Current Minimum Dynamic Output Current(4) Maximum Quiescent Supply Current Maximum 3-STATE Leakage Current 5.5 5.5 5.5 5.5 5.5 IOLD IOHD ICC (3) 4.0 ±0.25 40.0 ±2.5 IOZ Notes: 2. All outputs loaded; thresholds on input associated with output under test. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 4. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 5 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs DC Electrical Characteristics for ACT TA = +25°C Symbol VIH VIL VOH TA = –40°C to +85°C Units V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±2.5 1.5 75 –75 µA µA mA mA mA µA V Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 4.5 5.5 Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50 µA VIN = VIL or VIH: Typ. 1.5 1.5 1.5 5.5 4.49 5.49 2.0 2.0 0.8 1.5 4.4 5.4 Guaranteed Limits 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 IOH = –24mA IOH = –24mA(5) 0.001 0.001 VIN = VIL or VIH: IOL = 24mA IOL = 24mA(5) VI = VCC, GND VI = VIL, VIH; VO = VCC, GND VI = VCC – 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 0.6 IOUT = 50 µA 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 ±0.25 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 4.0 40.0 Notes: 5. All outputs loaded; thresholds on input associated with output under test. 6. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 6 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs AC Electrical Characteristics for AC TA = +25°C, CL = 50pF Symbol tPHL tPLH tPLH tPHL tPZL tPZH tPHZ tPLZ Output Disable Time TA = –40°C to +85°C, CL = 50pF Min. 2.5 1.5 2.5 2.0 2.5 1.5 1.0 1.0 Parameter Propagation Delay, Dn to On Propagation Delay, LE to On Output Enable Time VCC (V)(7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min. 0.5 1.5 2.5 2.0 2.5 1.5 1.0 1.0 Typ. 8.5 5.5 8.5 6.0 8.5 6.0 9.0 6.0 Max. 10.5 7.0 12.0 8.0 13.0 8.5 14.5 9.5 Max. 11.0 7.5 12.5 8.5 13.5 9.0 15.0 10.0 Units ns ns ns ns Note: 7. Voltage range 5.0 is 5.0V ± 0.5V. Voltage range 3.3 is 3.3V ± 0.3V. AC Operating Requirements for AC TA = +25°C, CL = 50pF Symbol tS tH tW TA = –40°C to +85°C, CL = 50pF Units ns ns ns 3.0 3.0 1.5 1.5 4.0 4.0 Parameter Setup Time, HIGH or LOW, Dn to LE Hold Time, HIGH or LOW, Dn to LE LE Pulse Width, HIGH VCC (V)(8) 3.3 5.0 3.3 5.0 3.3 5.0 Typ. 0 0 0 0 2.0 2.0 Guaranteed Minimum 3.0 3.0 1.5 1.5 4.0 4.0 Note: 8. Voltage range 5.0 is 5.0V ± 0.5V. Voltage range 3.3 is 3.3V ± 0.3V. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 7 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs AC Electrical Characteristics for ACT TA = +25°C, CL = 50pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ TA = –40°C to +85°C, CL = 50pF Min. 2.0 2.5 2.0 1.5 1.5 1.5 1.0 Parameter Propagation Delay, Dn to On Propagation Delay, LE to On Propagation Delay, LE to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time VCC (V)(9) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Min. 2.5 3.0 2.5 2.0 1.5 2.5 1.5 Typ. 6.0 6.0 5.5 5.5 5.5 6.5 5.0 Max. 10.5 10.5 9.5 10.0 9.5 11.0 8.5 Max. 12.0 12.0 10.5 11.0 10.5 12.5 9.5 Units ns ns ns ns ns ns ns Note: 9. Voltage range 5.0 is 5.0V ± 0.5V. AC Operating Requirements for ACT TA = +25°C, CL = 50pF Symbol tS tH tW TA = –40°C to +85°C, CL = 50pF Units ns ns ns 3.5 0 4.0 Parameter Setup Time, HIGH or LOW, Dn to LE Hold Time, HIGH or LOW, Dn to LE LE Pulse Width, HIGH VCC (V)(10) 5.0 5.0 5.0 Typ. 1.5 –1.5 2.0 Guaranteed Minimum 3.0 0 3.5 Note: 10. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance AC ACT Conditions VCC = OPEN VCC = 5.0V Typ. 5.0 25.0 42.0 Units pF pF ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 8 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 9 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 10 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 11 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 12 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.5 www.fairchildsemi.com 13