74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs
September 1988 Revised March 2005
74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D-type inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. The AC/ACT574 is functionally identical to the AC/ACT374 except for the pinouts.
Features
s ICC and IOZ reduced by 50% s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to AC/ACT374 s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s ACT574 has TTL-compatible inputs
Ordering Code:
Order Number 74AC574SC 74AC574SJ 74AC574MTC 74AC574PC 74ACT574SC 74ACT574SJ 74ACT574MTC 74ACT574PC Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B.
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009910
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74AC574 • 74ACT574
Logic Symbols
Pin Descriptions
Pin Names D0–D7 CP OE O0–O7 Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Description
IEEE/IEC
Function Table
Inputs OE H H H H L L L CP D H L H L H L H L H Internal Q NC NC L H L H NC NC Outputs ON Z Z Z Z L H NC NC Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data Function
H H
H
Connection Diagram
L
H H IGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition NC No Change
Functional Description
The AC/ACT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC574 • 74ACT574
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r50 mA r50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT¥ circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOZ Maximum Input Leakage Current Maximum 3-STATE Leakage Current IOLD IOHD ICC (Note 4) Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 4.0 75 mA mA 5.5 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 2 5 qC TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
V
IOH IOH IOH
12 mA 24 mA IOH 24 mA (Note 2)
50 PA VILor VIH 12 mA 24 mA 24 mA (Note 2) VCC, GND VIL, VIH VCC, VGND VCC, GND 1.65V 3.85V VCC or GND
V
IOUT VIN
0.44 0.44 0.44 V
IOL IOL IOL VI VI VO VOLD VOHD VIN
r0.1 r0.25
r1.0 r2.5
PA PA
VI (OE)
75
40.0
PA
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: M aximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC574 • 74ACT574
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT I]OLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 2 5 qC TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V IOUT VIN
50 PA
VILor VIH
V
IOH IOH
24 mA 24 mA (Note 5)
50 PA VILor VIH 24 mA 24 mA (Note 5) VCC, GND VIL, VIH VCC, GND VCC 2.1V 1.65V 3.85V VCC
V
IOUT VIN
V
IOL IOL
r0.1 r0.25
r1.0 r2.5
1.5 75
PA PA
mA mA mA
VI VI VO VI
VOLD VOHD VIN
75
40.0
PA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 7: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 75 95 3.5 2.0 3.5 2.0 2.5 2.0 3.0 2.0 3.5 2.0 2.0 1.0
25qC
50 pF Typ 112 153 8.5 6.0 7.5 5.5 7.0 5.0 6.5 5.0 7.5 6.0 5.5 4.5 13.5 9.5 12.0 8.5 11.0 8.5 10.5 8.0 12.0 9.5 9.0 7.5 Max
TA
40qC to 85qC
CL 50 pF Max MHz 15.0 11.0 13.5 9.5 12.0 9.0 11.5 9.0 13.0 10.5 10.0 8.5 ns ns ns ns ns ns Units
Min 60 85 3.5 2.0 3.5 2.0 2.5 2.0 3.0 1.5 2.5 1.5 1.5 1.0
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74AC574 • 74ACT574
AC Operating Requirements for AC
VCC Symbol tS tH tW Parameter Set-Up Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW
Note 8: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 0.5 0
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
(V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0
Guaranteed Minimum 2.5 1.5 1.5 1.5 6.0 4.0 3.0 2.0 1.5 1.5 7.0 5.0 ns ns ns
0.5
0 3.5 2.0
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 9) fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 2.0 2.0 2.0 2.0 6.4 6.0 7.0 5.5 9.5 9.0 10.5 8.5 1.5 1.5 1.5 1.5 10.0 10.0 11.5 9.0 ns ns ns ns 5.0 2.0 6.5 10.0 1.5 11.0 ns 5.0 5.0 Min 100 2.5 TA CL
25qC
50 pF Typ 110 7.0 11.0 Max
TA
40qC to 85qC
CL 50 pF Max ns 12.0 ns Units
Min 85 2.0
Note 9: Voltage Range 5.0 is 5.0V r0.5V
AC Operating Requirements for ACT
VCC Symbol tS tH tW Parameter Set-Up Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
TA CL
25qC
50 pF Typ 1.5
TA
40qC to 85qC
CL 50 pF Units
(V) (Note 10) 5.0 5.0 5.0
Guaranteed Minimum 2.5 1.0 4.0 ns ns ns
0.5
2.5
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 40.0 Units pF pF VCC VCC OPEN 5.0V Conditions
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74AC574 • 74ACT574
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74AC574 • 74ACT574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74AC574 • 74ACT574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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