74ACT825MTC

74ACT825 8-Bit D-Type Flip-Flop July 1988 Revised September 2000 74ACT825 8-Bit D-Type Flip-Flop General Description The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multiuse control of the interface. The ACT825 has noninverting outputs. Features s Outputs source/sink 24 mA s Inputs and outputs are on opposite sides s TTL compatible inputs Ordering Code: Order Number 74ACT825SC 74ACT825MTC 74ACT825SPC Package Number M24B MTC24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 O0–O7 OE1, OE2, OE3 EN CLR CP Description Data Inputs Data Outputs Output Enables Clock Enable Clear Clock Input FACT is a trademark of Fairchild Semiconductor. © 2000 Fairchild Semiconductor Corporation DS009895 www.fairchildsemi.com 74ACT825 Functional Description The ACT825 consists of eight D-type edge-triggered flipflops. These devices have 3-STATE outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs OE H H H L H L H H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Internal CP Output Function O Z Z Z L Z NC Z Z L H High-Z High-Z Clear Clear Hold Hold Load Load Load Load CLR X X L L H H H H H H EN L L X X H H L L L L   X X X Dn L H X X X X L H L H Q L H L L NC NC L H L H     X  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74ACT825 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C −0.5V to 7.0V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA +0.5V ± 50 mA ± 50 mA −65°C to +150°C Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 8.0 0.6 0.001 0.001 TA = 25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ± 0.1 ±0.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ± 1.0 ±5.0 1.5 75 −75 80 µA µA mA mA mA µA V V V V VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC −2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Units Conditions Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: M aximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT825 AC Electrical Characteristics VCC Symbol fMAX tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Propagation Delay CLR to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On Note 4: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Min 120 1.5 2.0 2.5 1.5 2.0 1.5 1.5 Typ 158 5.5 5.5 8.0 6.0 6.5 6.5 6.0 9.5 9.5 13.5 10.5 11.0 11.0 10.5 Max TA = −40°C to +85°C CL = 50 pF Min 109 1.5 1.5 2.0 1.5 1.5 1.5 1.5 10.5 10.5 15.5 11.5 12.0 12.0 11.5 Max MHz ns ns ns ns ns ns ns Units Parameter (V) (Note 4) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 AC Operating Requirements VCC Symbol tS tH tS tH tW Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW EN to CP Hold Time, HIGH or LOW EN to CP CP Pulse Width HIGH or LOW tW tREC CLR Pulse Width, LOW CLR to CP Recovery Time Note 5: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Typ 0.5 0 0 0 2.5 3.0 1.5 2.5 2.5 2.0 1.0 4.5 5.5 3.5 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 2.5 2.5 2.5 1.0 5.5 5.5 4.0 ns ns ns ns ns ns ns Units (V) (Note 5) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 44 Units pF pF VCC = OPEN VCC = 5.0V Conditions www.fairchildsemi.com 4 74ACT825 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74ACT825 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 www.fairchildsemi.com 6 74ACT825 8-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com