74ACT841SPC

74ACT841 10-Bit Transparent Latch with 3-STATE Outputs November 1988 Revised September 2000 74ACT841 10-Bit Transparent Latch with 3-STATE Outputs General Description The ACT841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The ACT841 is a 10-bit transparent latch, a 10-bit version of the ACT373. Features s ACT841 has TTL-compatible inputs s Outputs source/sink 24 mA s Non-inverting 3-STATE outputs Ordering Code: Order Number 74ACT841SC 74ACT841MTC 74ACT841SPC Package Number M24B MTC24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.) Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D9 O0–O9 OE LE Description Data Inputs 3-STATE Outputs Output Enable Latch Enable FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010156 www.fairchildsemi.com 74ACT841 Functional Description The ACT841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Function Table Inputs OE X H H H L L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Internal D X L H X L H X Q X L H NC L H NC Output Function O Z Z Z Z L H NC High Z High Z High Z Latched Transparent Transparent Latched LE X H H L H H L Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74ACT841 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150 °C Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 8.0 0.6 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 ±0.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±5.0 1.5 75 −75 80.0 µA µA µA mA mA µA V V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Units Conditions Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: M aximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT841 AC Electrical Characteristics VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Dn to On Propagation Delay Dn to On Propagation Delay LE to On Propagation Delay LE to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On Note 4: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Typ 5.5 5.5 5.5 5.5 5.5 5.5 6.0 6.0 Max 9.5 9.5 9.0 9.0 9.5 9.5 10.5 10.5 TA = −40°C to +85°C CL = 50 pF Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 10.0 10.0 10.0 10.0 10.5 10.5 11.0 11.0 ns ns ns ns ns ns ns ns Units (V) (Note 4) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 AC Operating Requirements VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH Note 5: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Typ −0.5 0.5 2.0 0.5 2.0 3.5 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 1.0 2.0 3.5 ns ns ns Units (V) (Note 5) 5.0 5.0 5.0 Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 44 Units pF pF Conditions VCC = OPEN VCC = 5.0V www.fairchildsemi.com 4 74ACT841 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74ACT841 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 www.fairchildsemi.com 6 74ACT841 10-Bit Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com