74ACTQ16543MTD

74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs December 1991 Revised December 1998 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs General Description The ACTQ16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The ACTQ16543 utilizes Fairchild Quiet Series™ technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector for superior performance. Features s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Independent registers for A and B buses s Separate controls for data flow in each direction s Back-to-back registers for storage Multiplexed real-time and stored data transfers s Separate control logic for each byte s 16-bit version of the ACTQ543 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250pF loads Ordering Code: Order Number 74ACTQ16543SSC 74ACTQ16543MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A0–A15 B0–B15 Descriptions A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010967.prf www.fairchildsemi.com 74ACTQ16543 Connection Diagram Pin Assignment for SSOP and TSSOP Functional Description The ACTQ16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable (CEABn) input must be LOW in order to enter data from A0–A15 or take data from B0–B15, as indicated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable (LEABn) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA n, LEBAn and OEBAn inputs. Data I/O Control Table Inputs CEABn H X L X L LEABn X H L X X OEABn X X X H L Latch Status (Byte n) Latched Latched Transparent — — Output Buffers (Byte n) High Z — — High Z Driving H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn www.fairchildsemi.com 2 74ACTQ16543 Logic Diagrams Byte 1 (0:7) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ACTQ16543 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Storage Temperature ±50 mA −65°C to +150°C −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA −20 mA +20 mA −0.5V to +7.0V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT™ circuits outside databook specifications. 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZT IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum I/O Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC Droop Minimum HIGH Dynamic Input Voltage Level Maximum LOW Dynamic Input Voltage Level Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 ±0.5 ±0.1 0.6 8.0 TA = −40°C to+85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VILor VIH 3.76 4.76 0.1 0.1 V V IOH = −24 mA IOH = −24 mA (Note 2) IOUT = 50 µA VIN = VILor VIH 0.44 0.44 ±5.0 ±1.0 1.5 80.0 75 −75 V µA µA mA µA mA mA V V V V V V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC − 2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) (Note 4)(Note 7) (Note 4)(Note 7) 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 5.0 5.0 0.5 −0.5 VOH + 1.0 VOH − 1.0 1.7 1.2 0.8 −0.8 VOH + 1.5 VOH − 1.8 2.0 0.8 www.fairchildsemi.com 4 74ACTQ16543 DC Electrical Characteristics (Continued) Note 5: M aximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW. Note 6: M aximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH. Note 7: M aximum number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V Input under test switching 3V to threshold (VILD). AC Electrical Characteristics VCC Symbol Parameter (V) (Note 8) tPLH tPHL tPLH tPHL tPZH tPZL Propagation Delay Transparent Mode An to Bnor Bn to An Propagation Delay LEBAn, LEABn to An, Bn Output Enable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn tPHZ tPLZ Output Disable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn Note 8: Voltage Range 5.0 is 5.0V ±0.5V. TA = +25°C CL = 50 pF Min 3.8 3.5 4.7 Typ 5.9 5.5 6.9 6.3 6.3 7.3 Max 8.3 7.9 9.8 9.0 9.2 10.3 TA = −40°C to +85°C CL = 50 pF Min 3.0 2.6 3.4 3.1 3.0 3.6 Max 9.0 8.5 10.8 9.8 9.9 10.3 ns ns ns Units 5.0 5.0 3.9 4.2 5.0 4.9 2.8 5.0 2.6 5.2 5.0 8.0 7.6 2.1 2.0 8.3 8.1 ns AC Operating Requirements VCC Symbol Parameter (V) (Note 9) tS tH tW Setup Time, HIGH or LOW An or Bn to LEBAn or LEABn Hold Time, HIGH or LOW An or Bn to LEBAn or LEABn Latch Enable, B to A Pulse Width, LOW Note 9: Voltage Range 5.0 is 5.0V ±0.5V TA = +25°C CL = 50 pF Typ 3.0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 3.0 ns Units 5.0 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns 5 www.fairchildsemi.com 74ACTQ16543 Extended AC Electrical Characteristics TA = −40 to +85°C VCC = Com Symbol Parameter CL = 50 pF 16 Outputs Switching (Note 10) Min tPLH tPHL tPLH tPHL tPZH tPZL Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBAn, LEABn to An, Bn Output Enable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn tPHZ tPLZ Output Disable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn tOSHL (Note 14) tOSLH (Note 14) tOSHL (Note 14) tOSLH (Note 14) tOST (Note 14) tOST (Note 14) Pin to Pin Skew HL Data to Output Pin to Pin Skew LH Data to Output Pin to Pin Skew Latch to Output Pin to Pin Skew Latch to Output Pin to Pin Skew Data to Output Pin to Pin Skew Latch to Output 2.2 1.0 ns ns 1.0 ns 2.6 ns 1.4 ns 1.1 ns 3.0 2.8 8.0 7.6 (Note 13) ns 4.3 3.7 4.0 4.3 11.3 9.7 10.7 11.3 (Note 12) ns 6.2 5.8 16.3 14.9 ns 4.5 3.7 Typ Max 11.1 9.6 Min 5.8 5.1 TA = −40 to +85°C VCC = Com CL = 250 pF (Note 11) Max 14.3 13.4 ns Units Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high, high-to-low, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 13: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation.Capacitance Typ 4.5 95.0 Units pF pF VCC = 5.0V VCC = 5.0V Conditions www.fairchildsemi.com 6 74ACTQ16543 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLVon the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case for active and enable transition. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability on the measurements. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 6. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit 7 www.fairchildsemi.com 74ACTQ16543 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (SSOP), JEDEC MO-153, 6.1mm Wide Package Number MS56A www.fairchildsemi.com 8 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.