74ACTQ373

74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs April 2007 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs Features ■ ICC and IOZ reduced by 50% ■ Guaranteed simultaneous switching noise level and tm General Description The ACQ/ACTQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the HIGH impedance state. The ACQ/ACTQ373 utilizes Fairchild Quiet Series™ technology to guarantee quiet output switching and improve dynamic threshold performance. features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Improved latch up immunity ■ Eight latches in a single package ■ 3-STATE outputs drive bus lines or buffer memory address registers ■ Outputs source/sink 24mA ■ Faster prop delays than the standard AC/ACT373 Ordering Information Order Number 74ACQ373SC 74ACQ373SJ 74ACTQ373SC 74ACTQ373SJ 74ACQT373QSC Package Number M20B M20D M20B M20D MQA20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin Descriptions Pin Names D0–D7 LE OE O0–O7 Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs Description FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation. ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs Logic Symbol Functional Description The ACQ/ACTQ373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. IEEE/IEC Truth Table Inputs LE X H H L Outputs Dn X L H X OE H L L L On Z L H O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 2 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 3 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Supply Voltage DC Input Diode Current VI = –0.5V VI = VCC + 0.5V VI IOK DC Input Voltage DC Output Diode Current VO = –0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage Parameter Rating –0.5V to +7.0V –20mA +20mA –0.5V to VCC + 0.5V –20mA +20mA –0.5V to VCC + 0.5V ±50mA ±50mA –65°C to +150°C ±300mA 140°C DC Output Source or Sink Current Storage Temperature DC Latch-Up Source or Sink Current Junction Temperature ICC or IGND DC VCC or Ground Current per Output Pin Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Supply Voltage ACQ ACTQ VI VO TA ∆V / ∆t ∆V / ∆t Input Voltage Output Voltage Operating Temperature Parameter Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC –40°C to +85°C 125mV/ns 125mV/ns Minimum Input Edge Rate, ACQ Devices: VIN from 30% to 70% of VCC, VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate, ACTQ Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 4 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs DC Electrical Characteristics for ACQ TA = +25°C TA = –40°C to +85°C Symbol VIH Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 –75 4.0 ±0.25 40.0 ±2.5 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 Units V VIL Maximum LOW Level Input Voltage V VOH Minimum HIGH Level Output Voltage V VIN = VIL or VIH: 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 VIN = VIL or VIH 3.0 4.5 5.5 IIN(3) IOLD IOHD ICC (3) IOH = –12mA IOH = –24mA IOH = –24mA(1) 0.002 0.001 0.001 IOL = 12 mA IOL = 24 mA IOL = 24 mA(1) VI = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND VI (OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND Figures 1 & 2(4) Figures 1 & 2(4) (5) IOUT = 50µA 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 V Maximum Input Leakage Current Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current Maximum 3-STATE Leakage Current Quiet Output Maximum Dynamic VOL Quiet Output Maximum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 µA mA mA µA µA IOZ VOLP VOLV VIHD VILD 5.0 5.0 5.0 5.0 1.1 –0.6 3.1 1.9 1.5 –1.2 3.5 1.5 V V V V (5) Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 4. Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. 5. Max number of data inputs (n) switching. (n–1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1MHz. ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 5 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs DC Electrical Characteristics for ACTQ TA = +25°C TA = –40°C to +85°C Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA VIN = VIL or VIH: Typ. 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±2.5 ±0.25 Units V V V 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 IOH = –24mA IOH = –24mA(6) 0.001 0.001 VIN = VIL or VIH: IOL = 24 mA IOL = 24 mA(6) VI = VCC, GND VI = VIL, VIH, VO = VCC, GND VI = VCC – 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC, or GND Figures 1 & 2(8) Figures 1 & 2(8) (9) 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 IOUT = 50µA V 4.5 5.5 IIN (3) Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(7) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 µA µA mA mA mA µA V V V V IOZ ICCT IOLD IOHD ICC (3) 0.6 1.5 75 –75 4.0 40.0 VOLP VOLV VIHD VILD 1.1 –0.6 1.9 1.2 1.5 –1.2 2.2 0.8 (9) Notes: 6. All outputs loaded; thresholds on input associated with output under test. 7. Maximum test duration 2.0ms, one output loaded at a time. 8. Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. 9. Max number of data inputs (n) switching. (n–1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 6 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs AC Electrical Characteristics for ACQ TA = +25°C, CL = 50pF Symbol tPHL, tPLH tPHL, tPLH tPZL, tPZH tPHZ, tPLZ TA = –40°C to +85°C, CL = 50pF Min. 2.5 1.5 2.5 2.0 2.5 1.5 1.0 1.0 Parameter Propagation Delay, Dn to On Propagation Delay, LE to On Output Enable Time Output Disable Time VCC (V)(10) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min. 2.5 1.5 2.5 2.0 2.5 1.5 1.0 1.0 Typ. 8.0 5.5 8.0 6.0 8.5 6.5 9.0 6.5 1.0 0.5 Max. 10.5 7.0 12.0 8.0 13.0 8.5 14.5 9.5 1.5 1.0 Max. 11.0 7.5 12.5 8.5 13.5 9.0 15.0 10.0 1.5 1.0 Units ns ns ns ns ns tOSHL, tOSLH Output to Output Skew, Dn to On(11) Note: 10. Voltage range 5.0 is 5.0V ± 0.5V. Voltage range 3.3 is 3.3V ± 0.3V. 11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements for ACQ TA = +25°C, CL = 50pF Symbol tS tH tW TA = –40°C to +85°C, CL = 50 pF Guaranteed Minimum Units ns ns ns 3.0 3.0 1.5 1.5 4.0 4.0 Parameter Setup Time, HIGH or LOW, Dn to LE Hold Time, HIGH or LOW, Dn to LE LE Pulse Width, HIGH VCC (V)(12) 3.3 5.0 3.3 5.0 3.3 5.0 Typ. 0 0 0 0 2.0 2.0 3.0 3.0 1.5 1.5 4.0 4.0 Note: 12. Voltage range 5.0 is 5.0V ± 0.5V. Voltage range 3.3 is 3.3V ± 0.3V. ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 7 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs AC Electrical Characteristics for ACTQ TA = +25°C, CL = 50pF Symbol tPHL, tPLH tPHL, tPLH tPZL, tPZH tPHZ, tPLZ tOSHL, tOSLH TA = –40°C to +85°C, CL = 50pF Min. 2.0 2.5 2.0 1.0 Parameter Propagation Delay, Dn to On Propagation Delay, LE to On Output Enable Time Output Disable Time Output to Output Skew, Dn to On(14) VCC (V)(13) 5.0 5.0 5.0 5.0 5.0 Min. 2.0 2.5 2.0 1.0 Typ. 6.5 7.0 7.0 8.0 0.5 Max. 7.5 8.5 9.0 10.0 1.0 Max. 8.0 9.0 9.5 10.5 1.0 Units ns ns ns ns ns Notes: 13. Voltage range 5.0 is 5.0V ± 0.5V. 14. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements for ACTQ TA = +25°C, CL = 50pF Symbol tS tH tW TA = –40°C to +85°C, CL = 50 pF Units ns ns ns 3.0 1.5 4.0 Parameter Setup Time, HIGH or LOW, Dn to LE Hold Time, HIGH or LOW, Dn to LE LE Pulse Width, HIGH VCC (V)(15) 5.0 5.0 5.0 Typ. 0 0 2.0 Guaranteed Minimum 3.0 1.5 4.0 Note: 15. Voltage range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Conditions VCC = OPEN VCC = 5.0V Typ. 4.5 44.0 Units pF pF ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 8 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/V OHV: ■ Determine the quiet output pin that demonstrates the Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50pF, 500Ω. 2. Deskew the HFS generator so that no two channels have greater than 150ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. ■ Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. ■ Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: ■ Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. ■ First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. ■ Next decrease the input HIGH voltage level, VIH until the output begins to oscillate or steps out a min of 2ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. ■ Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Notes: 16. VOHV and VOLP are measured with respect to ground reference. 17. Input pulses have the following characteristics: f = 1MHz, tr = 3ns, tf = 3ns, skew < 150ps. Figure 1. Quiet Output Noise Voltage Waveforms Figure 2. Simultaneous Switching Test Circuit ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 9 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 10 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 11 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 5. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 12 74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. ActiveArray Bottomless Build it Now CoolFET CROSSVOLT CTL™ Current Transfer Logic™ DOME 2 E CMOS ® EcoSPARK EnSigna FACT Quiet Series™ ® FACT ® FAST FASTr FPS ® FRFET GlobalOptoisolator GTO ® HiSeC i-Lo ImpliedDisconnect IntelliMAX ISOPLANAR MICROCOUPLER MicroPak MICROWIRE MSX MSXPro OCX OCXPro ® OPTOLOGIC ® OPTOPLANAR PACMAN POP ® Power220 ® Power247 PowerEdge PowerSaver ® PowerTrench Programmable Active Droop ® QFET QS QT Optoelectronics Quiet Series RapidConfigure RapidConnect ScalarPump SMART START ® SPM STEALTH™ SuperFET SuperSOT -3 SuperSOT -6 SuperSOT -8 SyncFET™ TCM ® The Power Franchise ™ TinyLogic TINYOPTO TinyPower TinyWire TruTranslation SerDes ® UHC UniFET VCX Wire ® TinyBoost TinyBuck DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1989 Fairchild Semiconductor Corporation 74ACQ373, 74ACTQ373 Rev. 1.3 www.fairchildsemi.com 13