74ACTQ374PCX

74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs July 1989 Revised November 1999 74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs General Description The ACQ/ACTQ374 is a high-speed, low-power octal Dtype flip-flop featuring separate D-type inputs for each flipflop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The ACQ/ACTQ374 utilizes FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Features s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Buffered positive edge-triggered clock s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT374 Ordering Code: Order Number 74ACQ374SC 74ACQ374SJ 74ACQ374PC 74ACTQ374SC 74ACTQ374SJ 74ACTQ374QSC 74ACTQ374PC Package Number M20B M20D N20A M20B M20D MQA20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names D0 – D7 CP OE O0–O7 Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Description FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010238 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 Logic Symbols Functional Description The ACQ/ACTQ374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. IEEE/IEC Truth Table Inputs Dn H L X CP Outputs OE L L H On H L Z   X H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74ACQ374 • 74ACTQ374 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) PDIP 140°C ±50 mA −65°C to +150 °C ±300 mA ±50 mA −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V −0.5V to +7.0V Recommended Operating Conditions Supply Voltage (VCC) ACQ ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t ACQ Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate ∆V/∆t ACTQ devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics for ACQ Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOLD IOHD IOZ Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum 3-STATE Leakage Current VOLP Quiet Output Maximum Dynamic VOL 5.5 5.0 1.1 ±0.25 1.5 ±2.5 µA V 5.5 5.5 5.5 5.5 4.0 0.002 0.001 0.001 TA = +25°C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 TA = −40°C to +85°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 −75 40.0 µA mA mA µA V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Figure 1, Figure 2 (Note 5)(Note 6) V IOUT = 50 µA V IOH = −12 mA IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V Units Conditions VOUT = 0.1V or VCC − 0.1V ICC (Note 4) Maximum Quiescent Supply Current 3 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 DC Electrical Characteristics for ACQ Symbol VOLV VIHD VILD Parameter Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.0 5.0 3.1 1.9 VCC (V) 5.0 Typ −0.6 (Continued) TA = −40°C to +85°C Guaranteed Limits −1.2 V Figure 1, Figure 2 (Note 5)(Note 6) 3.5 1.5 V V (Note 5)(Note 7) (Note 5)(Note 7) TA = +25°C Units Conditions Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 5: DIP Package. Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. Note 7: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. DC Electrical Characteristics for ACTQ Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN (Note 4) Maximum Input Leakage Current IOZ ICCT IOLD IOHD ICC (Note 4) VOLP VOLV VIHD VILD Maximum 3-STATE Current Maximum ICC/Input (Note 4) Minimum Dynamic Output Current (Note 8) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 1.1 −0.6 1.9 1.2 4.0 1.5 −1.2 2.2 0.8 0.6 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 ±0.25 2.0 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±2.5 1.5 75 −75 40.0 µA µA mA mA mA µA V V V V V Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 8) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 8) VI = VCC, GND VI = VIL, V IH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Figure 1, Figure 2 (Note 10)(Note 11) Figure 1, Figure 2 (Note 10)(Note 11) (Note 10)(Note 12) (Note 10)(Note 12) Note 8: All outputs loaded; thresholds on input associated with output under test. Note 9: Maximum test duration 2.0 ms, one output loaded at a time. Note 10: DIP package. Note 11: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND Note 12: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 4 74ACQ374 • 74ACTQ374 AC Electrical Characteristics for ACQ VCC Symbol fMAX tPLH tPHL tPZL tPZH tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 14) CP to On Voltage Range 3.3 is 3.3V ± 0.3V Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. TA = +25°C CL = 50 pF Min 75 90 3.0 2.0 3.0 2.0 1.0 1.0 9.5 6.5 9.5 6.5 9.5 8.0 1.0 0.5 13.0 8.5 13.0 8.5 14.5 9.5 1.5 1.0 Typ Max TA = −40°C to +85°C CL = 50 pF Min 70 85 3.0 2.0 3.0 2.0 1.0 1.0 13.5 9.0 13.5 9.0 15.0 10.0 1.5 1.0 Max MHz ns ns ns ns Units Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Output Disable Time (V) (Note 13) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Note 13: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACQ VCC Symbol Parameter (V) (Note 15) tS tH tW Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width, HIGH or LOW Note 15: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V TA = +25°C CL = 50 pF Typ 0 0 0 2.0 2.0 2.0 3.0 3.0 1.5 1.5 4.0 4.0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 3.0 3.0 1.5 1.5 4.0 4.0 ns ns ns Units 3.3 5.0 3.3 5.0 3.3 5.0 AC Electrical Characteristics for ACTQ VCC Symbol fMAX tPLH tPHL tPZL tPZH tPHZ tPLZ tOSHL tOSLH Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Output Disable Time Output to Output Skew (Note 17) CP to On (V) (Note 16) 5.0 5.0 5.0 5.0 5.0 Min 85 2.0 2.0 1.0 7.0 7.5 8.0 0.5 9.0 9.0 10.0 1.0 TA = +25°C CL = 50 pF Typ Max TA = −40°C to +85°C CL = 50 pF Min 80 2.0 2.0 1.0 9.5 9.5 10.5 1.0 Max MHz ns ns ns ns Units Note 16: Voltage Range 5.0 is 5.0V ± 0.5V Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. 5 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 AC Operating Requirements for ACTQ VCC Symbol tS tH tH Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width, HIGH or LOW Note 18: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Typ 0 0 2.0 3.0 1.5 4.0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 3.0 1.5 4.0 ns ns ns Units (V) (Note 18) 5.0 5.0 5.0 Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 42.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions www.fairchildsemi.com 6 74ACQ374 • 74ACTQ374 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Note 19: VOHV and VOLP are measured with respect to ground reference. Note 20: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit 7 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B www.fairchildsemi.com 8 74ACQ374 • 74ACTQ374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 9 www.fairchildsemi.com 74ACQ374 • 74ACTQ374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide Package Number MQA20 www.fairchildsemi.com 10 74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com