74ALVC16245_05

74ALVC16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs October 2001 Revised May 2005 74ALVC16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs General Description The ALVC16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The 74ALVC16245 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC16245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V–3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD 3.0 ns max for 3.0V to 3.6V VCC 3.5 ns max for 2.3V to 2.7V VCC 6.0 ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model ! 2000V Machine model !200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74ALVC16245G (Note 2)(Note 3) 74ALVC16245MTD (Note 3) Package Number BGA54A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: Ordering code “G” indicates Trays. Note 3: D evices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation DS500678 www.fairchildsemi.com 74ALVC16245 Connection Diagrams Pin Assignment of TSSOP Pin Descriptions Pin Names OEn T/Rn A0–A15 B0–B15 NC Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs No Connect FBGA Pin Assignments 1 A B C D E F G H J B0 B2 B4 B6 B8 B10 B12 B14 B15 2 NC B1 B3 B5 B7 B9 B11 B13 NC 3 T/R1 NC VCC GND GND GND VCC NC T/R2 4 OE1 NC VCC GND GND GND VCC NC OE2 5 NC A1 A3 A5 A7 A9 A11 A13 NC 6 A0 A2 A4 A6 A8 A10 A12 A14 A15 Truth Tables Pin Assignment for FBGA OE1 L L H Inputs OE2 L L H (Top Thru View) T/R2 L H X Outputs Bus B8–B15 Data to Bus A8–A15 Bus A8–A15 Data to Bus B8–B15 HIGH Z State on A8–A15, B8–B15 Inputs T/R1 L H X Outputs Bus B0–B7 Data to Bus A0–A7 Bus A0–A7 Data to Bus B0–B7 HIGH Z State on A0–A7, B0–B7 H H IGH Voltage Level L LOW Voltage Level X Immaterial (HIGH or LOW, inputs and I/O’s may not float) Z High Impedance Logic Diagram www.fairchildsemi.com 2 74ALVC16245 Absolute Maximum Ratings(Note 4) Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) (Note 5) DC Input Diode Current (IIK) VI  0V DC Output Diode Current (IOK) VO  0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG) 0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA 50 mA r50 mA r100 mA 65qC to 150qC Recommended Operating Conditions (Note 6) Power Supply Operating Input Voltage Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused control inputs must be held HIGH or LOW. 1.65V to 3.6V 0V to VCC 0V to VCC 40qC to 85qC DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH IOH IOH IOH Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 VCC - 0.2 1.2 2.0 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 V V V V Max Units 100 PA 4 mA 6 mA 12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II IOZ ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 24 mA 100 PA 4 mA 6 mA 12 mA 24 mA 3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 3.6 3.6 0 3.6 3 - 3.6 0 d VI d 3.6V 0 d VO d 3.6V VI VIH V CC or GND, IO VCC  0.6V r5.0 r10 40 750 PA PA PA PA 'ICC 3 www.fairchildsemi.com 74ALVC16245 AC Electrical Characteristics TA Symbol Parameter VCC Min tPHL, tPLH tPZL, tPZH tPLZ, tPHZ Propagation Delay Output Enable Time Output Disable Time 1.3 1.3 1.3 CL 3.3V r 0.3V Max 3 4.3 4.2 50 pF VCC Min 1.5 1.5 1.5 2.7V Max 3.5 5.4 4.7 VCC Min 1.0 1.0 1.0 40qC to 85qC, RL 500: CL 2.5V r 0.2V Max 3.0 4.9 4.2 30 pF VCC Min 1.5 1.5 1.5 1.8V r 0.15V Max 6.0 9.3 7.6 ns ns ns Units Capacitance Symbol CIN CIO CPD Input Capacitance Input, Output Capacitance Power Dissipation Capacitance Parameter VI VO Outputs Enabled f Conditions 0V or VCC 0V or VCC 10 MHz, CL 50 pF TA VCC 3.3 3.3 3.3 2.5 25qC Typical 6 7 20 20 Units pF pF pF www.fairchildsemi.com 4 74ALVC16245 AC Loading and Waveforms TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f 1MHz; tr tf 2ns; ZO Symbol Vmi Vmo VX VY VL VCC 3.3V r 0.3V 1.5V 1.5V VOL  0.3V VOH  0.3V 6V 2.7V 1.5V 1.5V VOL  0.3V VOH  0.3V 6V 2.5 r 0.2V VCC/2 VCC/2 VOL  0.15V VOH  0.15V VCC*2 1.8V r 0.15V VCC/2 VCC/2 VOL  0.15V VOH  0.15V VCC*2 50:) FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic 5 www.fairchildsemi.com 74ALVC16245 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 6 74ALVC16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com