74ALVCH16240

74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver September 2001 Revised February 2002 74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold General Description The ALVCH16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH16240 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating inputs at a valid logic level. The 74ALVCH16240 is designed for low voltage (1.65V to 3.6V) VCC applications with output capability up to 3.6V. The 74ALVCH16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD 3.9 ns max for 3.0V to 3.6V VCC 5.3 ns max for 2.3V to 2.7V VCC 6.0 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number 74ALVCH16240T Package Number MTD48 Package Descriptions 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn I0–I15 O0–O15 Description Output Enable Input (Active LOW) Bushold Inputs Outputs © 2002 Fairchild Semiconductor Corporation DS500629 www.fairchildsemi.com 74ALVCH16240 Connection Diagram Truth Tables Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H Inputs OE4 L L H I12–I15 L H X I8–I11 L H X I4–I7 L H X Outputs O8–O11 H L Z Outputs O12–O15 H L Z I0–I3 L H X Outputs O4–O7 H L Z Outputs O0–O3 H L Z H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Functional Description The 74ALVCH16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. Logic Diagram www.fairchildsemi.com 2 74ALVCH16240 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG) −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions (Note 3) Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed, limited to 4.6V. Note 3: Floating or unused control inputs must be held HIGH or LOW. 1.65V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = −100 µA IOH = −4 mA IOH = −6 mA IOH = −12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA II II(HOLD) Input Leakage Current Bushold Input Minimum Drive Hold Current 0 ≤ VI ≤ 3.6V VIN = 0.58V VIN = 1.07V VIN = 0.7V VIN = 1.7V VIN = 0.8V VIN = 2.0V 0 < VO ≤ 3.6V IOZ ICC ∆ICC 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 ≤ VO ≤ 3.6V VI = V CC or GND, IO = 0 VIH = VCC − 0.6V 3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 3.6 1.65 1.65 2.3 2.3 3.0 3.0 3.6 3.6 3.6 3 - 3.6 25 −25 45 −45 75 −75 ±500 ±10 40 750 µA µA µA µA VCC - 0.2 1.2 2.0 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 ±5.0 µA V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units 3 www.fairchildsemi.com 74ALVCH16240 AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter CL = 50 pF VCC = 3.3V ± 0.3V Min tPHL, tPLH tPZL, tPZH tPLZ, tPHZ Propagation Delay Output Enable Time Output Disable Time 1.0 1.0 1.0 Max 3.9 5 4.4 VCC = 2.7V Min Max 5.3 6.1 4.8 CL = 30 pF VCC = 2.5V ± 0.2V Min 1.0 1.0 1.0 Max 5.3 6.4 5.4 VCC = 1.8V ± 0.15V Min 1.5 1.5 1.5 Max 6.0 8.2 6.8 ns ns ns Units Capacitance Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Control Data Conditions VI = 0V or VCC VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 50 pF Outputs Disabled f = 10 MHz, CL = 50 pF TA = +25°C VCC 3.3 3.3 3.3 3.3 2.5 3.3 2.5 Typical 3 6 7 19 16 5 4 pF pF pF Units www.fairchildsemi.com 4 74ALVCH16240 AC Loading and Waveforms TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω) Symbol Vmi Vmo VX VY VL VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC*2 1.8V ± 0.15V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC*2 FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic 5 www.fairchildsemi.com 74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com