74F109

74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number 74F109SC 74F109SJ 74F109PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009471 www.fairchildsemi.com 74F109 Truth Table Inputs SD L H L H H H H H CD H L L H H H H H CP X X J X X X I h I h X K X X X I I h h X Q H Q Q H L H L Toggle Q L Q Outputs Q L H H H     X L H (h) = HIGH Voltage Level L (l) = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.  Unit Loading/Fan Out U.L. Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Data Inputs Clock Pulse Inputs (Active Rising Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Description 1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 50/33.3 Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.8 mA 20 µA/−1.8 mA −1 mA/20 mA Q1, Q2, Q1, Q2 Outputs Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F109 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with Vcc = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to VCC −0.5V to +5.5V −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −65°C to +150 °C −55°C to +125 °C −55°C to +175 °C Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 5% VCC VOL IIH IBVI ICEX VID Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test 4.75 Output Leakage 3.75 Circuit Current IIL Input LOW Current −0.6 −1.8 IOS ICC Output Short-Circuit Current Power Supply Current −60 11.7 −150 17.0 V 0.0 10% VCC 2.5 V 2.7 0.5 5.0 7.0 50 V µA µA µA Min Max Max Max Min Min 2.0 0.8 −1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA All Other Pins Grounded IOD µA mA mA mA mA 0.0 Max Max Max Max VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Jn, Kn) VIN = 0.5V (CDn, SDn) VOUT = 0V CP = 0V 3 www.fairchildsemi.com 74F109 AC Electrical Characteristics TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn o r Q n 100 3.8 4.4 3.2 3.5 VCC = +5.0V CL = 50 pF Typ 125 5.3 6.2 5.2 7.0 7.0 8.0 7.0 9.0 Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 90 3.8 4.4 3.2 3.5 8.0 ns 9.2 8.0 10.5 ns ns Max MHz Units AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn CPn Pulse Width HIGH or LOW CDn or SDn Pulse Width LOW Recovery Time 2.0 CDn or SDn to CP 2.0 ns 3.0 3.0 1.0 1.0 4.0 5.0 4.0 Max TA = 0°C to +70°C VCC = +5.0V Min 3.0 3.0 ns 1.0 1.0 4.0 ns 5.0 4.0 ns Max Units www.fairchildsemi.com 4 74F109 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 5 www.fairchildsemi.com 74F109 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74F109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com