74F113

74F113 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Asynchronous input: LOW input to SD sets Q to HIGH level Set is independent of clock Ordering Code: Order Number 74F113SC 74F113SJ 74F113PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1 999 Fairchild Semiconductor Corporation DS009473 www.fairchildsemi.com 74F113 Unit Loading/Fan Out U.L. Pin Names J1, J2, K1, K2 CP1, CP2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Set Inputs (Active LOW) Outputs Description HIGH/LOW 1.0/1.0 1.0/4.0 1.0/5.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−2.4 mA 20 µA/−3.0 mA −1 mA/20 mA Truth Table Inputs SD L H H H H H (h) = H IGH Voltage Level L (l) = L OW Voltage level ] = HIGH-to-LOW Clock Transition X = Immaterial Q 0 ( Q 0) = Before HIGH-to-LOW Transition of Clock Outputs J X h l h l K X h h l l Q H Q0 L H Q0 Q L Q0 H L Q0 CP     X  Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F113 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to VCC −0.5V to +5.5V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70 °C +4.5V to +5.5V Note 1: A bsolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: E ither voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 4.75 3.75 −0.6 −2.4 −3.0 IOZH IOZL IOS ICC Output Leakage Current Output Leakage Current Output Short-Circuit Current Power Supply Current −60 12 50 −50 −150 19 µA µA mA mA Max Max Max Max mA Max 5.0 7.0 50 µA µA µA V µA Max Max Max 0.0 0.0 VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Jn, Kn) VIN = 0.5V (CPn) VIN = 0.5V (SDn) VOUT = 2.7V VOUT = 0.5V VOUT = 0V 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 V Min Min 2.0 0.8 −1.2 Typ Max Units V V V V Min Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IOL = 20 mA 3 www.fairchildsemi.com 74F113 AC Electrical Characteristics TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay SDn to Qn or Qn 85 2.0 2.0 2.0 2.0 VCC = +5.0V CL = 50 pF Typ 105 4.0 4.0 4.5 4.5 6.0 6.0 6.5 6.5 Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 80 2.0 2.0 2.0 2.0 7.0 7.0 7.5 7.5 Max MHz ns Units ns AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn CPn Pulse Width HIGH or LOW SDn Pulse Width, LOW SDn to CPn Recovery Time 4.0 3.0 0 0 4.5 4.5 4.5 4.0 Max TA = 0°C to +70°C VCC = +5.0V Min 5.0 3.5 0 0 5.0 ns 5.0 5.0 5.0 ns ns ns Max Units www.fairchildsemi.com 4 74F113 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74F113 Dual JK Negative Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com