74F163A

74F161A, 74F163A Synchronous Presettable Binary Counter April 2007 74F161A, 74F163A Synchronous Presettable Binary Counter Features ■ Synchronous counting and loading ■ High-speed synchronous expansion ■ Typical count frequency of 120MHz tm General Description The 74F161A and 74F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters. The 74F161A has an asynchronous Master-Reset input that overrides all other inputs and forces the outputs LOW. The 74F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. The 74F161A and 74F163A are high-speed versions of the 74F161 and 74F163. Ordering Information Order Number 74F161ASC 74F161ASJ 74F161APC 74F163ASC 74F163ASJ 74F163APC Package Number M16A M16D N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagrams 74F161A 74F163A ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 74F161A, 74F163A Synchronous Presettable Binary Counter Logic Symbols 74F161A IEEE/IEC 74F163A IEEE/IEC 74F161A 74F163A Unit Loading/Fan Out Pin Names CEP CET CP MR (74F161A) SR (74F163A) P0–P3 PE Q0–Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output U.L. HIGH / LOW 1.0 / 1.0 1.0 / 2.0 1.0 / 1.0 1.0 / 1.0 1.0 / 2.0 1.0 / 1.0 1.0 / 2.0 50 / 33.3 50 / 33.3 Input IIH / IIL Output IOH / IOL 20µA / -0.6mA 20µA / -1.2mA 20µA / -0.6 mA 20µA / -0.6 mA 20µA / -1.2 mA 20µA / -0.6 mA 20µA / -1.2mA -1mA / 20mA -1mA / 20mA ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 2 74F161A, 74F163A Synchronous Presettable Binary Counter Functional Description The 74F161A and 74F163A count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 74F161A) occur as a result of, and synchronous with, the LOW-toHIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (74F161A), synchronous reset (74F163A), parallel load, count-up and hold. Five control inputs—Master Reset (MR, 74F161A), Synchronous Reset (SR, 74F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)— determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR ('F161A) or SR (74F163A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The 74F161A and 74F163A use D-type edge triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15. To implement synchronous multi-stage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the 74F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET Mode Select Table SR(1) L H H H H PE X L H H H CET CEP X X H L X X X H X L Action on the Rising Clock Edge ( ) Reset (Clear) Load (Pn→Qn) Count (Increment) No Change (Hold) No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: 1. For 74F163A only State Diagram ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 3 74F161A, 74F163A Synchronous Presettable Binary Counter Block Diagram ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 Figure 1. www.fairchildsemi.com 4 74F161A, 74F163A Synchronous Presettable Binary Counter Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol TSTG TA TJ VCC VIN IIN VO Storage Temperature Parameter Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage(2) Input Current(2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max.) ESD Last Passing Voltage (Min.) Rating –65°C to +150°C –55°C to +125°C –55°C to +150°C –0.5V to +7.0V –0.5V to +7.0V –30mA to +5.0mA –0.5V to VCC –0.5V to +5.5V twice the rated IOL (mA) 4000V Note: 2. Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol TA VCC Free Air Ambient Temperature Supply Voltage Parameter Rating 0°C to +70°C +4.5V to +5.5V ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 5 74F161A, 74F163A Synchronous Presettable Binary Counter DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 10% VCC 5% VCC 10% VCC VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal Min. 2.0 Typ. Max. Units V 0.8 –1.2 V V V 0.5 5.0 7.0 50 V µA µA µA V 3.75 –0.6 –1.2 µA mA mA mA Min. Min. Min. Max. Max. Max. 0.0 0.0 Max. Max. Max. IIN = –18mA 2.5 2.7 IOL = 20mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9µA, All Other Pins Grounded VIOD = 150mV, All Other Pins Grounded VIN = 0.5V (CEP, CP, MR, P0–P3) VIN = 0.5V (CET, PE, SR) VOUT = 0.0V –60 37 4.75 Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Voltage –150 55 ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 6 74F161A, 74F163A Synchronous Presettable Binary Counter AC Electrical Characteristics TA = +25°C, VCC = +5.0V, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Parameter Maximum Count Frequency Propagation Delay, CP to Qn (PE Input HIGH) Propagation Delay, CP to Qn (PE Input LOW) Propagation Delay, CP to TC Propagation Delay, CET to TC Propagation Delay, MR to Qn (74F161A) Propagation Delay, MR to TC (74F161A) Min. 3.5 3.5 4.0 4.0 5.0 5.0 2.5 2.5 5.5 4.5 TA = –55°C to +125°C, TA = 0°C to 70°C, VCC = +5.0V, VCC = +5.0V, CL = 50pF CL = 50pF Typ. Max. Min. Max. Min. Max. Units 100 5.5 7.5 6.0 6.0 10.0 10.0 4.5 4.5 9.0 8.0 7.5 10.0 8.5 8.5 14.0 14.0 7.5 7.5 12.0 10.5 3.5 3.5 4.0 4.0 5.0 5.0 2.5 2.5 5.5 4.5 9.0 11.5 10.0 10.0 16.5 15.5 9.0 9.0 14.0 12.5 3.5 3.5 4.0 4.0 5.0 5.0 2.5 2.5 5.5 4.5 8.5 11.0 9.5 9.5 15.0 15.0 8.5 8.5 13.0 11.5 ns ns ns ns ns MHz ns AC Operating Requirements TA = +25°C, VCC = +5.0V Symbol tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(H) tW(L) tW(L) tREC TA = –55°C to +125°C, TA = 0°C to 70°C, VCC = +5.0V VCC = +5.0V Min. 5.5 5.5 2.5 2.5 13.5 10.5 3.6 0 13.0 6.0 0 0 5.0 5.0 5.0 8.0 5.0 6.0 Parameter Setup Time, HIGH or LOW, Pn to CP Hold Time, HIGH or LOW, Pn to CP Setup Time, HIGH or LOW, PE or SR to CP Hold Time, HIGH or LOW, PE or SR to CP Setup Time, HIGH or LOW, CEP or CET to CP Hold Time, HIGH or LOW, CEP or CET to CP Clock Pulse Width (Load), HIGH or LOW Clock Pulse Width (Count), HIGH or LOW MR Pulse Width, LOW (74F161A) Recovery Time, MR to CP (74F161A) Min. 5.0 5.0 2.0 2.0 11.0 8.5 2.0 0 11.0 5.0 0 0 5.0 5.0 4.0 6.0 5.0 6.0 Max. Max. Min. 5.0 5.0 2.0 2.0 11.5 9.5 2.0 0 11.5 5.0 0 0 5.0 5.0 4.0 7.0 5.0 6.0 Max. Units ns ns ns ns ns ns ns ns ns ns ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 7 74F161A, 74F163A Synchronous Presettable Binary Counter Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 8 74F161A, 74F163A Synchronous Presettable Binary Counter Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 9 74F161A, 74F163A Synchronous Presettable Binary Counter Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 10 74F161A, 74F163A Synchronous Presettable Binary Counter TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Rev. 1.0.2 www.fairchildsemi.com 11