74F194SC

74F194 4-Bit Bidirectional Universal Shift Register April 1988 Revised March 2000 74F194 4-Bit Bidirectional Universal Shift Register General Description The 74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. Features s Typical shift frequency of 150 MHz s Asynchronous master reset s Hold (do nothing) mode s Fully synchronous serial or parallel data transfers Ordering Code: Order Number 74F194SC 74F194SJ 74F194PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009498 www.fairchildsemi.com 74F194 Unit Loading/Fan Out Pin Names S0 , S1 P0–P3 DSR DSL CP MR Q0–Q3 Description Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F194 contains four edge-triggered D-type flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data (P0–P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW. Mode Select Table Operating Mode Reset Hold Shift Left Shift Right Parallel Load Inputs Outputs MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 L H H H H H H X l h h l l h X l l l h h h X X X X l h X X X l h X X X X X X X X X L L L L L H q0 q1 q2 q3 q1 q2 q3 q1 q2 q3 L H q0 q1 q2 q0 q1 q2 pn p0 p1 p2 p3 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level pn (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F194 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to VCC −0.5V to +5.5V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current −60 33 4.75 3.75 −0.6 −150 46 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 µA µA µA V µA mA mA mA Max Max Max 0.0 0.0 Max Max Max Min 2.0 0.8 −1.2 Typ Max Units V V V V Min Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 0V 3 www.fairchildsemi.com 74F194 AC Electrical Characteristics TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPHL Maximum Shift Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn 105 3.5 3.5 4.5 VCC = +5.0V CL = 50 pF Typ 150 5.2 5.5 8.6 7.0 7.0 12.0 Max TA = −55°C to +125°C VCC = +5.0V CL = 50 pF Min 90 3.0 3.0 4.5 8.5 8.5 14.5 Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 90 3.5 3.5 4.5 8.0 8.0 14.0 Max MHz ns ns Units AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tREC Setup Time, HIGH or LOW Pn or DSR or DSL to CP Hold Time, HIGH or LOW Pn or DSR or DSL to CP Setup Time, HIGH or LOW Sn to CP Hold Time, HIGH or LOW Sn to CP CP Pulse Width, HIGH MR Pulse Width, LOW Recovery Time MR to CP 4.0 4.0 1.0 0 10.0 8.0 0 0 5.0 5.0 9.0 Max TA = −55°C to +125°C VCC = +5.0V Min 6.0 4.0 1.5 1.0 10.5 8.0 0 0 5.5 5.0 9.0 Max TA = 0°C to +70°C VCC = +5.0V Min 4.0 4.0 1.0 1.0 11.0 8.0 0 0 5.5 5.0 11.0 ns ns ns ns ns Max Units www.fairchildsemi.com 4 74F194 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com 74F194 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74F194 4-Bit Bidirectional Universal Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com