74F245

74F245 Octal Bidirectional Transceiver with 3-STATE Outputs April 1988 Revised March 2005 74F245 Octal Bidirectional Transceiver with 3-STATE Outputs General Description The 74F245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 24 mA at the A Ports and 64 mA at the B Ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active HIGH) enables data from A Ports to B Ports; Receive (active LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B Ports by placing them in a High Z condition. Features s Non-inverting buffers s Bidirectional data path s A outputs sink 24 mA s B outputs sink 64 mA Ordering Code: Order Number 74F245SC 74F245SC_NL (Note 1) 74F245SJ 74F245MSA 74F245MTC 74F245PC 74F245PC_NL (Note 1) Package Number M20B M20B M20D MSA20 MTC20 N20A N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pb-Free 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated. Logic Symbols IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS009503 www.fairchildsemi.com 74F245 Connection Diagram Unit Loading/Fan Out U.L. Pin Names OE T/R A0–A7 Description HIGH/LOW Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs 1.0/2.0 1.0/2.0 3.5/1.083 150/40(38.3) 3.5/1.083 Input IIH/IIL Output IOH/IOL 20 PA/1.2 mA 20 PA/1.2 mA 70 PA/0.65 mA 3 mA/24 mA (20 mA) 70 PA/0.65 mA 600/106.6(80) 12 mA/64 mA (48 mA) Truth Table Inputs Output OE L L H H HIGH Voltage Level L LOW Voltage Level X Immaterial T/R L H X Bus B Data to Bus A Bus A Data to Bus B High Z State www.fairchildsemi.com 2 74F245 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V 0V) 65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0qC to 70qC 4.5V to 5.5V 0.5V to VCC 0.5V to 5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC VOL IIH IBVI IBVIT ICEX VID IOD Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current IIL IIH  IOZH IIL  IOZL IOS IZZ ICCH ICCL ICCZ Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 70 95 85 4.75 3.75 10% VCC 10% VCC 2.4 2.0 2.7 0.5 0.55 5.0 7.0 0.5 50 V Min Max Max Max Max 0.0 0.0 Max Max Max Max 0.0V Max Max Max V Min Min 2.0 0.8 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN IOH IOH IOH IOL IOL VIN VIN VIN VOUT IID VIOD 1.2 18 mA 3 mA (An) 15 mA (Bn) 3 mA (An) 24 mA (An) 64 mA (Bn) 2.7V 7.0V (OE , T/R) 5.5 V (An, Bn) VCC (An, Bn) 1.9 PA 150 mV PA PA mA PA V All Other Pins Grounded All Other Pins Grounded VIN VOUT VOUT VOUT VOUT VOUT VO VO VO 0.5V (T/R, OE) 2.7V (An, Bn) 0.5V (An, Bn) 0V (An) 0V (Bn) 5.25V(An, Bn) HIGH LOW HIGH Z PA mA 1.2 70 PA PA mA 650 60 100 150 225 500 90 120 110 PA mA mA mA 3 www.fairchildsemi.com 74F245 AC Electrical Characteristics TA Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 2.5 2.5 3.0 3.5 2.0 2.0 VCC CL 25qC 5.0V 50 pF Typ 4.2 4.2 5.3 6.0 5.0 5.0 Max 6.0 6.0 7.0 8.0 6.5 6.5 TA  55qC to 125qC CL 50 pF TA 0qC to 70qC CL 50 pF Units Min 2.0 2.0 2.5 3.0 2.0 2.0 Max 7.5 7.5 9.0 10.0 9.0 10.0 Min 2.0 2.0 2.5 3.0 2.0 2.0 Max 7.0 7.0 8.0 9.0 7.5 7.5 ns ns www.fairchildsemi.com 4 74F245 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74F245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74F245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com 74F245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 8 74F245 Octal Bidirectional Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com