74F269SPC

74F269 8-Bit Bidirectional Binary Counter April 1988 Revised September 2000 74F269 8-Bit Bidirectional Binary Counter General Description The 74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock. Features s Synchronous counting and loading s Built-in lookahead carry capability s Count frequency 100 MHz s Supply current 113 mA typ s 300 mil slimline package Ordering Code: Order Number 74F269SC 74F269SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Function Table PE L CEP X CET X U/D X CP H H H H H X L L X H L L X X H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = Transition LOW-to-HIGH      Function Parallel Load All Flip-Flops Hold Hold (TC Held HIGH) Count Up Count Down  © 2000 Fairchild Semiconductor Corporation DS009510 www.fairchildsemi.com 74F269 Unit Loading/Fan Out U.L. Pin Names P0–P7 PE U/D CEP CET CP TC Q0–Q7 Description HIGH/LOW Parallel Data Inputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Input Terminal Count Output (Active LOW) Flip-Flop Outputs 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 5.0/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA Logic Diagram www.fairchildsemi.com 2 74F269 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to VCC −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current Power Supply Current −60 104 113 4.75 3.75 −0.6 −150 125 135 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 −1.2 Typ Max Units V V V V V µA µA µA V µA mA mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA, All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 0V VO = HIGH VO = LOW 3 www.fairchildsemi.com 74F269 AC Electrical Characteristics TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn (Count-Up) Propagation Delay U/D to TC Propagation Delay CET to TC Propagation Delay CP to TC Propagation Delay CP to Qn (Count-Down) Propagation Delay CP to Qn (Load) 100 3.5 4.5 3.5 4.5 3.5 3.0 4.5 5.0 3.5 4.5 3.5 4.0 8.0 10.5 7.5 7.5 7.0 10.5 10.0 10.0 10.5 10.5 7.0 7.0 VCC = +5.0V CL = 50 pF Typ Max TA = 0°C to +70°C VCC = 5.0V CL = 50 pF Min 85 3.5 4.5 3.5 4.5 3.5 3.0 4.5 4.5 3.5 4.5 3.5 4.0 7.0 11.0 10.0 11.0 10.5 11.5 10.5 10.5 11.0 11.0 10.0 7.0 Max MHz ns ns ns ns ns ns Units AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tS(H) tS(L) tH(H) tH(L) Setup Time, HIGH or LOW U/D to CP Hold Time, HIGH or LOW U/D to CP Setup Time, HIGH or LOW Data to CP Hold Time, HIGH or LOW Data to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CET or CEP to CP Hold Time, HIGH or LOW CET or CEP to CP Clock Pulse Width, HIGH or LOW 3.5 3.0 1.0 1.0 5.5 5.5 0 0 6.0 8.0 0 0 3.5 3.5 8.0 6.0 0.0 0.0 Max TA = 0°C to +70°C VCC = 5.0V Min 4.0 3.0 2.0 1.0 6.5 6.5 0 0 6.5 9.0 0 0 3.5 4.0 9.5 7.0 0.0 0.0 ns ns ns ns ns ns Max Units www.fairchildsemi.com 4 74F269 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74F269 8-Bit Bidirectional Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com