74F564

74F564 Octal D-Type Flip-Flop with 3-STATE Outputs April 1983 Revised October 2000 74F564 Octal D-Type Flip-Flop with 3-STATE Outputs General Description The 74F564 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is sorted in the flip-flops on the LOW-to-HIGH Clock (CP) transition. This device is functionally identical to the 74F574, but has inverted outputs. Features s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F574 s 3-STATE outputs for bus-oriented applications Ordering Code: Order Number 74F564SJ 74F564PC Package Number M20D N20A Package Description 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009563 www.fairchildsemi.com 74F564 Unit Loading/Fan Out Pin Names D0 – D7 CP OE O0–O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) 3-STATE Outputs Description U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 150/40 (33.3) −3 mA/24 mA (20 mA) Functional Description The 74F564 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table Inputs OE H H H H L L L L CP H D L H L H L H L H Internal Outputs Function Q NC NC H L H L NC NC O Z Z Z Z H L NC NC Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data     H H H H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial  Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F564 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to VCC −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current 55 −60 4.75 3.75 −0.6 50 −50 −150 500 86 10% VCC 2.5 2.4 2.7 2.7 0.5 5.0 7.0 50 V µA µA µA V µA mA µA µA mA µA mA Min Max Max Max 0.0 0.0 Max Max Max Max 0.0V Max V Min Min 2.0 0.8 −1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −3 mA IOH = −1 mA IOH = −3 mA IOL = 24 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V VO = HIGH Z 3 www.fairchildsemi.com 74F564 AC Electrical Characteristics TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 100 2.5 2.5 3.0 3.0 1.5 1.5 5.2 5.9 5.6 6.2 3.4 2.7 8.5 8.5 9.0 9.0 5.5 5.5 VCC = +5.0V CL = 50 pF Typ Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 70 2.5 2.5 2.5 2.5 1.5 1.5 8.5 8.5 10.0 10.0 6.5 6.5 ns Max MHz ns Units AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW 2.0 2.5 2.0 2.0 5.0 5.0 Max TA = 0°C to +70°C VCC = +5.0V Min 2.0 2.5 2.0 2.0 5.0 5.0 ns ns Max Units www.fairchildsemi.com 4 74F564 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74F564 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com