74F657

74F657 Octal Bidirectional Transceiver with March 1988 Revised August 1999 74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description The 74F657 contains eight non-inverting buffers with 3STATE outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A Port and 64 mA at the B Port. Features s 300 Mil 24-pin slimline DIP s Combines 74F245 and 74F280A functions in one package s 3-STATE outputs s B Outputs sink 64 mA s 12 mA source current, B side s Input diodes for termination effects Ordering Code: Order Number 75F657SC 74F657SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009584 www.fairchildsemi.com 74F657 Unit Loading/Fan Out U.L. Pin Names A0–A7 Description HIGH/LOW Data Inputs/ 3-STATE Outputs B0–B7 Data Inputs/ 3-STATE Outputs T/R OE PARITY Transmit/Receive Input Enable Input Parity Input/ 3-STATE Output ODD/EVEN ERROR ODD/EVEN Parity Input Error Output 4.5/0.15 150/40 (33.3) 3.5/0.117 600/106.6 (80) 2.0/0.067 2.0/0.067 3.5/0.117 600/106.6 (80) 1.0/0.033 600/106.6 (80) Input IIH/IIL Output IOH/IOL 90 µA/− 90 µA −3 mA/24 mA (20 mA) 70 µA/−70 µA −12 mA/64 mA (48 mA) 40 µA/−40 µA 40 µA/−40 µA 70 µA/−70µA −12 mA/64 mA (48 mA) 20 µA/−20 µA −12 mA/64 mA (48 mA) Functional Description The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from the A Port to the B Port; Receive (active LOW) enables data from the B Port to the A Port. The Output Enable (OE) input disables the parity and ERROR outputs and both the A and B Ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH. When transmitting (T/R HIGH), the parity generator detects whether an even or odd number of bits on the A Port are HIGH and compares these with the condition of the parity select (ODD/EVEN). If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH. In receiving mode (T/R LOW), the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error. Function Table Number of Inputs that are HIGH 0, 2, 4, 6, 8 Inputs OE T/R L L L L L L 1, 3, 5, 7 L L L L L L Immaterial H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Function Table Input/ Output Outputs OE Outputs Mode Transmit Transmit Receive Receive Receive Receive Transmit Transmit Receive Receive Receive Receive Z L L H H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Inputs Outputs T/R L H X Bus B Data to Bus A Bus A Data to Bus B High-Z State ODD/ EVEN H L H H L L H L H H L L X Parity ERROR H L H L H L L H H L H L Z Z Z H L L H Z Z L H H L Z H H L L L L H H L L L L X www.fairchildsemi.com 2 74F657 Functional Block Diagram 3 www.fairchildsemi.com 74F657 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to VCC −0.5V to +5.5V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 10% VCC 5% VCC 5% VCC VOL Output LOW Voltage IIH Input HIGH Current IBVI IBVIT IIL Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current IOZH IOZL IIH + IOZH IIL + IOZL IOS Output Leakage Current Output Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current ICEX Output HIGH Leakage Current −60 −100 10% VCC 10% VCC 2.5 2.4 2.0 2.7 2.7 0.5 0.55 20 40 100 1.0 2.0 −20 −40 50 −50 70 90 −70 −90 −150 −225 250 1.0 2.0 IZZ ICCH ICCL ICCZ Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 101 112 109 500 125 150 145 V µA µA mA µA µA µA µA µA mA µA mA mA µA mA mA mA Min V Min Min 2.0 0.8 −1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA (An) IOH = −3 mA (An B n, Parity, ERROR) IOH = −15 mA (Bn, Parity, ERROR) IOH = −1 mA (An) IOH = −3 mA (An, B n, Parity, ERROR) IOL = 24 mA (An) IOL = 64 mA (Bn Parity, ERROR) VIN = 2.7V (ODD/EVEN) VIN 2.7V (T/R, OE) VIN = 7.0V (T/R, OE, ODD/EVEN) VIN = 5.5V (Parity, Bn) VIN = 5.5V (An) VIN = 0.5V (ODD/EVEN) VIN = 0.5V (T/R, OE) VOUT = 2.7V (ERROR) VOUT = 0.5V (ERROR) VI/O = 2.7V (Bn, Parity) VI/O = 2.7V (An) VI/O = 0.5V (Bn, Parity) VI/O = 0.5V (An) VOUT = 0V (An) VOUT = 0V (Bn, Parity, ERROR) VOUT = VCC (ERROR) VOUT = VCC (Bn, Parity) VOUT = VCC (An) VOUT = 5.25V (An, Bn, Parity, ERROR) VO = HIGH VO = LOW VO = HIGH Z Max VCC = 0 Max Max Max Max Max Max Max Max Max Max 0.0V Max Max Max www.fairchildsemi.com 4 74F657 AC Electrical Characteristics TA = +25°C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay An to Bn, Bn to An Propagation Delay An to Parity Propagation Delay ODD/EVEN to PARITY Propagation Delay ODD/EVEN to ERROR Propagation Delay Bn to ERROR Propagation Delay PARITY to ERROR Output Enable Time OE to An/Bn Output Disable Time OE to An/Bn Output Enable Time OE to ERROR (Note 3) Output Disable Time OE to ERROR Output Enable Time OE to PARITY Output Disable Time OE to PARITY 2.5 3.0 6.5 7.0 4.5 4.5 4.5 4.5 8.0 8.0 7.0 7.5 3.0 4.0 1.0 1.0 3.0 4.0 1.0 1.0 3.0 4.0 1.0 1.0 VCC = +5.0V CL = 50 pF Typ 4.5 4.9 10.1 10.9 7.8 8.8 7.5 8.2 14.0 15.0 10.8 11.8 5.0 6.5 4.5 4.9 5.0 7.7 4.5 4.9 5.0 7.7 4.6 5.1 Max 8.0 7.5 14.0 15.0 11.0 12.0 11.0 12.0 20.5 21.5 15.5 16.5 8.0 10.0 8.0 7.5 8.0 10.0 8.0 7.5 8.0 10.0 8.0 7.5 TA = −55°C to +125°C VCC = +5.0V CL = 50 pF Min 2.5 3.0 5.5 5.5 4.0 4.5 4.0 4.5 7.5 7.5 6.0 6.5 2.5 3.5 1.0 1.0 2.5 3.5 1.0 1.0 2.5 3.5 1.0 1.0 Max 9.5 8.5 18.0 20.5 14.0 16.5 14.0 16.5 27.0 28.5 20.0 22.0 11.0 13.5 9.5 8.5 11.0 13.5 9.5 8.5 11.0 13.5 9.5 8.5 TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 2.5 3.0 6.0 6.0 4.0 4.5 4.0 4.5 7.5 7.5 6.0 7.5 2.5 3.5 1.0 1.0 2.5 3.5 1.0 1.0 2.5 3.5 1.0 1.0 Max 9.0 8.0 16.0 16.5 13.0 13.5 13.0 13.5 23.0 23.5 17.0 18.5 9.5 11.0 9.0 8.0 9.5 11.0 9.0 8.0 9.5 11.0 9.0 8.0 ns ns ns Units ns ns ns ns ns ns ns ns ns Note 3: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) + (Output Enable Time). 5 www.fairchildsemi.com 74F657 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74F657 Octal Bidirectional Transceiver with Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com