74F828

74F827 • 74F828 10-Bit Buffers/Line Drivers April 1988 Revised February 2004 74F827 • 74F828 10-Bit Buffers/Line Drivers General Description The 74F827 and 74F828 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility. The 74F828 is an inverting version of the 74F827. Features s 3-STATE output s 74F828 is inverting Ordering Code: Order Number 74F827SC (Note 1) 74F827SPC 74F828SC 74F828SPC (Note 1) Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: D evices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F827 74F828 © 2004 Fairchild Semiconductor Corporation DS009598 www.fairchildsemi.com 74F827 • 74F828 Logic Symbols 74F827 74F828 IEEE/IEC 74F827 IEEE/IEC 74F828 Unit Loading/Fan Out Pin Names OE1, OE2 D0–D7 O0–O7 Description Output Enable Input Data Inputs Data Outputs, 3-STATE U.L. HIGH/LOW 1.0/1.0 1.0/1.0 600/106.6 (80) Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA −12 mA/64 mA (48 mA) Functional Description The 74F827 and 74F828 are line drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. The devices have 3-STATE outputs controlled by the Output Enable (OE) pins. The outputs can sink 64 mA and source 15 mA. Input clamp diodes limit high-speed termination effects. Function Table Inputs OE L L H Dn 74F827 H L X H L Z Outputs On 74F828 L H Z Transparent Transparent High Z Function H = H IGH Voltage level L = LOW Voltage Level Z = High Impedance X = Immaterial www.fairchildsemi.com 2 74F827 • 74F828 Logic Diagrams 74F827 74F828 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F827 • 74F828 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −65°C to +150 °C −55°C to +125 °C −55°C to +150 °C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to VCC −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCH ICCL ICCZ ICCH ICCL ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current (74F827) Power Supply Current (74F827) Power Supply Current (74F827) Power Supply Current (74F828) Power Supply Current (74F828) Power Supply Current (74F828) 30 60 40 14 56 35 −100 4.75 3.75 −0.6 50 −50 −225 500 45 90 60 20 85 50 10% VCC 10% VCC 5% VCC 10% VCC 2.4 2.0 2.7 0.55 5.0 7.0 50 V µA µA µA V µA mA µA µA mA µA mA mA mA mA mA mA Min Max Max Max 0.0 0.0 Max Max Max Max 0.0V Max Max Max Max Max Max V Min Min 2.0 0.8 −1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −3 mA IOH = −15 mA IOH = −3 mA IOL = 64 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V VO = HIGH VO = LOW VO = HIGH Z VO = HIGH VO = LOW VO = HIGH Z www.fairchildsemi.com 4 74F827 • 74F828 AC Electrical Characteristics TA = +25°C Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Output (74F827) Propagation Delay Data to Output (74F828) Output Enable Time OE to On Output Disable Time OE to On 1.0 1.5 1.0 1.0 3.0 3.5 1.5 1.0 VCC = +5.0V CL = 50 pF Typ 3.0 3.3 3.0 2.0 5.7 6.8 3.3 3.5 Max 5.5 5.5 5.0 4.0 9.0 11.5 8.0 8.0 2.5 3.0 1.5 1.0 10.0 12.5 9.0 9.0 TA = −55°C to +125°C VCC = +5.0V CL = 50 pF Min 1.0 1.5 Max 7.5 7.0 TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 1.0 1.5 1.0 1.0 2.5 3.0 1.5 1.0 Max 6.5 6.0 5.5 4.0 9.5 12.0 8.5 8.5 ns ns ns ns Units 5 www.fairchildsemi.com 74F827 • 74F828 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B www.fairchildsemi.com 6 74F827 • 74F828 10-Bit Buffers/Line Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com