74LCX16543

74LCX16543 Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and Outputs May 1995 Revised April 2001 74LCX16543 Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and Outputs General Description The LCX16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The LCX16543 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16543 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 5.2 ns tPD max (VCC = 3.3V), 20 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s ±24 mA Output Drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human Body Model > 2000V Machine Model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX16543MEA 74LCX16543MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol © 2001 Fairchild Semiconductor Corporation DS012464 www.fairchildsemi.com 74LCX16543 Pin Descriptions Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A0–A15 B0–B15 Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs Data I/O Control Table Inputs CEABn H X L X L LEABn X H L X X OEABn X X X H L Latch Status (Byte n) Latched Latched Transparent — — Output Buffers (Byte n) High Z — — High Z Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn Functional Description The LCX16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable (CEABn) input must be LOW in order to enter data from A0–A15 or take data from B0–B15, as indicated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable (LEABn) input makes the A-to-B latches transparent; a subsequent LOWto-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBAn, LEBAn and OEBAn inputs. www.fairchildsemi.com 2 74LCX16543 Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LCX16543 Absolute Maximum Ratings(Note 2) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI < GND VO < GND VO > VCC V mA mA mA mA mA −0.5 to +7.0 −0.5 to +7.0 −0.5 to +7.0 −0.5 to VCC + 0.5 −50 −50 +50 ±50 ±100 ±100 −65 to +150 °C Recommended Operating Conditions (Note 4) Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V − 3.6V VCC = 2.7V − 3.0V VCC = 2.3V − 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V ±24 ±12 ±8 −40 0 85 10 mA °C ns/V ∆t/∆V Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Unused (inputs or I/Os) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −8 mA IOH = −12 mA IOH = −18 mA IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF Input Leakage Current 3-STATE I/O Leakage Power-Off Leakage Current 0 ≤ VI ≤ 5.5V 0 ≤ VO ≤ 5.5V VI = VIH or VIL VI or VO = 5.5V Conditions VCC (V) 2.3 − 2.7 2.7 − 3.6 2.3 − 2.7 2.7 − 3.6 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 − 3.6 0 VCC − 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 ±5.0 ±5.0 10 µA µA µA V V TA = −40°C to +85°C Min 1.7 2.0 0.7 0.8 Max Units V V www.fairchildsemi.com 4 74LCX16543 DC Electrical Characteristics Symbol ICC ∆ICC Parameter Quiescent Supply Current Increase in ICC per Input (Continued) VCC (V) 2.3 − 3.6 2.3 − 3.6 2.3 − 3.6 TA = −40°C to +85°C Min Max 20 ±20 500 µA µA Conditions VI = V CC or GND 3.6V ≤ VI, VO ≤ 5.5V (Note 5) VIH = VCC −0.6V Units Note 5: Outputs in disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500 Ω Symbol Parameter VCC = 3.3V ± 0.3V CL = 50 pF Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Propagation Delay An to Bn or Bn to An Propagation Delay LEBAn to An or LEABn to Bn Output Enable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn Output Disable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn Setup Time, HIGH or LOW, Data to LEXXn Hold Time, HIGH or LOW, Data to LEXXn Pulse Width, Latch Enable, LOW Output to Output Skew (Note 6) 3.0 1.0 1.0 3.0 3.5 1.5 1.5 2.0 1.5 1.5 2.5 6.5 6.5 1.5 1.5 2.5 7.0 7.0 1.5 1.5 3.0 7.8 7.8 ns ns ns ns ns 1.5 1.5 6.5 6.5 1.5 1.5 7.0 7.0 1.5 1.5 8.5 8.5 ns 1.5 1.5 1.5 1.5 Max 5.2 5.2 6.5 6.5 VCC = 2.7V CL = 50 pF Min 1.5 1.5 1.5 1.5 Max 6.0 6.0 7.5 7.5 VCC = 2.5V ± 0.2V CL = 30 pF Min 1.5 1.5 1.5 1.5 Max 6.2 6.2 7.8 7.8 ns ns Units Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25°C Typical 0.8 0.6 −0.8 −0.6 Units V V Capacitance Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF 5 www.fairchildsemi.com 74LCX16543 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V trise and tfall 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V www.fairchildsemi.com 6 74LCX16543 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com 74LCX16543 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A www.fairchildsemi.com 8 74LCX16543 Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com