74LCX32373

Preliminary 74LCX32373 Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs (Preliminary) January 2001 Revised August 2001 74LCX32373 Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs (Preliminary) General Description The LCX32373 contains thirty-two non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LCX32373 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features I 5V tolerant inputs and outputs I 2.3V–3.6V VCC specifications provided I 5.4 ns tPD max (VCC = 3.3V), 20 µA ICC max I Power down high impedance inputs and outputs I Supports live insertion/withdrawal (Note 1) I ±24 mA output drive (VCC = 3.0V) I Uses patented noise/EMI reduction circuitry I Latch-up performance exceeds 500 mA I ESD performance: Human body model > 2000V Machine model > 200V I Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX32373GX (Note 2) Package Number BGA96A (Preliminary) Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 2: BGA package available in Tape and Reel only. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500547 www.fairchildsemi.com Preliminary 74LCX32373 Connection Diagram Pin Descriptions Pin Names OEn LEn I0 - I31 O0 - O31 Description Output Enable Input (Active LOW) Latch Enable Input Inputs Outputs FBGA Pin Assignments 1 A B C D E F G H (Top Thru View) J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3 OE1 GND VCC GND GND VCC GND OE2 OE3 GND VCC GND GND VCC GND OE4 4 LE1 GND VCC GND GND VCC GND LE2 LE3 GND VCC GND GND VCC GND LE4 5 I0 I2 I4 I6 I8 I10 I12 I15 I16 I18 I20 I22 I24 I26 I28 I31 6 I1 I3 I5 I7 I9 I11 I13 I14 I17 I19 I21 I23 I25 I27 I29 I30 Truth Table Inputs LEn X H H L OEn H L L L In X L H X Outputs On Z L H O0 H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description The LCX32373 contains thirty-two D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 32-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. www.fairchildsemi.com 2 Preliminary 74LCX32373 Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com Preliminary 74LCX32373 Absolute Maximum Ratings(Note 3) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC V mA mA mA mA mA −0.5 to +7.0 −0.5 to +7.0 −0.5 to +7.0 −0.5 to VCC + 0.5 −50 −50 +50 ±50 ±100 ±100 −65 to +150 °C Recommended Operating Conditions (Note 5) Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V − 3.6V VCC = 2.7V − 3.0V VCC = 2.3V − 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V ±24 ±12 ±8 −40 0 85 10 mA °C ns/V ∆t/∆V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = 8 mA IOH = −12 mA IOH = −18 mA IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current 0 ≤ VI ≤ 5.5V 0 ≤ VO ≤ 5.5V VI = VIH or VIL VI or VO = 5.5V Conditions VCC (V) 2.3 − 2.7 2.7 − 3.6 2.3 − 2.7 2.7 − 3.6 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 − 3.6 0 VCC − 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 ±5.0 ±5.0 10 µA µA µA V V TA = −40°C to +85°C Min 1.7 2.0 0.7 0.8 Max Units V V www.fairchildsemi.com 4 Preliminary 74LCX32373 DC Electrical Characteristics Symbol ICC ∆ICC Parameter Quiescent Supply Current Increase in ICC per Input (Continued) VCC (V) 2.3 − 3.6 2.3 − 3.6 2.3 − 3.6 TA = −40°C to +85°C Min Max 20 ±20 500 µA µA Conditions VI = V CC or GND 3.6V ≤ VI, VO ≤ 5.5V (Note 6) VIH = VCC −0.6V Units Note 6: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V CL = 50 pF Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW Setup Time, In to LE Hold Time, In to LE LE Pulse Width Output Disable Time Propagation Delay In t o O n Propagation Delay LE to On Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 Max 5.4 5.4 5.5 5.5 6.1 6.1 6.0 6.0 VCC = 2.7V CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 Max 5.9 5.9 6.4 6.4 6.5 6.5 6.3 6.3 VCC = 2.5V ± 0.2V CL = 30 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 Max 6.5 6.5 6.6 6.6 7.9 7.9 7.2 7.2 ns ns ns ns ns ns ns Units Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25°C Typical 0.8 0.6 −0.8 −0.6 V V Units Capacitance Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF 5 www.fairchildsemi.com Preliminary 74LCX32373 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V trise and tfall 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V www.fairchildsemi.com 6 Preliminary 74LCX32373 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com Preliminary 74LCX32373 Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Preliminary Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com