74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
October 2000 Revised March 2005
74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
General Description
The 74LCXZ245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V and 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The T/R input determines the direction of data flow through the device. The OE input disables both the A and B ports by placing them in a high impedance state. The 74LCXZ245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. When VCC is between 0V and 1.5V, the 74LCXZ245 is on the high impedance state during power up or power down. This places the outputs in the high impedance (Z) state preventing intermittent low impedance loading or glitching in bus oriented applications.
Features
s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 7.0 ns tPD max (VCC
3.3V), 10 PA ICC max
s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s r24 mA output drive (VCC
3.0V)
s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:
Human body model ! 2000V Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCXZ245WM 74LCXZ245SJ 74LCXZ245MSA 74LCXZ245MTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OE T/R A0–A7 B0–B7 Description Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
© 2005 Fairchild Semiconductor Corporation
DS500362
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74LCXZ245
Truth Table
Inputs Outputs OE L L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Note 2: Unused bus terminals during HIGH Z State must be held HIGH or LOW.
T/R L H X Bus B0 – B7 Data to Bus A0 – A7 Bus A0 – A7 Data to Bus B0 – B7 HIGH Z State on A0 – A7, B0 – B7 (Note 2)
Logic Diagram
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74LCXZ245
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC V mA mA mA mA mA
0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150
qC
Recommended Operating Conditions (Note 5)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC VCC VCC TA Free-Air Operating Temperature Input Edge Rate, VIN 0.8V 2.0V, VCC 3.0V 3.0V 3.6V 2.7V - 3.0V 2.3V - 2.7V Parameter Operating Min 2.7 0 0 0 Max 3.6 5.5 VCC 5.5 Units V V V
r24 r12 r8 40
0 85 10
mA
qC
ns/V
't/'V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: U nused inputs or I/O pins must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II IOZ IOFF IPU/PD Input Leakage Current 3-STATE I/O Leakage Power-Off Leakage Current Power Up/ Power Down 3-STATE Output Current Conditions VCC (V) 2.3 2.7 2.7 3.6 2.3 2.7 2.7 - 3.6 TA
40qC to 85qC
Max
Min 1.7 2.0
Units V
0.7 0.8 VCC 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55
V
100 PA 8 mA 12 mA 18 mA 24 mA
100 PA 8mA 12 mA 16 mA 24 mA
2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 3.6 0 0 1.5
V
V
0 d VI d 5.5V 0 d VO d 5.5V VI VO VI V IH or VIL 5.5V to VCC V CC or GND VI or VO
r5.0 r5.0
10
PA PA PA PA
r5.0
3
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74LCXZ245
DC Electrical Characteristics
Symbol ICC Parameter Quiescent Supply Current Increase in ICC per Input VI VIH
(Continued)
VCC (V) VCC or GND VCC 0.6V 2.3 3.6 2.3 3.6 2.3 3.6 TA
Conditions
40qC to 85qC
Max 225
Units
Min
3.6V d VI, VO d 5.5V (Note 6)
r225
500
PA PA
'ICC
Note 6: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA Symbol Parameter VCC CL Min tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output to Output Skew (Note 7) Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5
40qC to 85qC, RL
50 pF Max 7.0 7.0 8.5 8.5 7.5 7.5 1.0 1.0 CL Min 1.5 1.5 1.5 1.5 1.5 1.5
500: 2.7V 50 pF Max 8.0 8.0 9.5 9.5 8.5 8.5 ns ns ns ns Units
3.3V r 0.3V
VCC
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL 50 pF, VIH 30 pF, VIH 50 pF, VIH 30 pF, VIH Conditions 3.3V, VIL 2.5V, VIL 3.3V, V IL 2.5V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 2 5 qC 0.8 0.6 Typical Units V V
0.8 0.6
Capacitance
Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 25 Units pF pF pF
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74LCXZ245
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.7V 1.5V 1.5V VOL 0.3V VOH 0.3V
trise and tfall
2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
5
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74LCXZ245
Schematic Diagram Generic for LCX Family
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74LCXZ245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74LCXZ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74LCXZ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
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74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
