74LVQ240

74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs June 1993 Revised June 2001 74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description The LVQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. Features s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75Ω s 4 kV minimum ESD immunity Ordering Code: Order Number 74LVQ240SC 74LVQ240SJ 74LVQ240QSC Package Number M20B M20D MQA20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Pin Descriptions Pin Names OE1, OE2 I0–I7 O0–O7 Description 3-STATE Output Enable Inputs Inputs Outputs Truth Tables Inputs OE1 In L H X Inputs OE2 L L H H = HIGH Voltage Level X = Immaterial Outputs (Pins 12, 14, 16, 18) H L Z Outputs In L H X L = LOW Voltage Level Z = High Impedance Connection Diagram L L H (Pins 3, 5, 7, 9) H L Z © 2001 Fairchild Semiconductor Corporation DS011611 www.fairchildsemi.com 74LVQ240 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±400 mA −65°C to +150°C ±300 mA Recommended Operating Conditions (Note 2) Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN 0.8V to 2.0V VCC @ 3.0V 125 mV/ns 2.0V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN IOLD IOHD ICC IOZ Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Maximum 3-STATE Leakage Current VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage 3.6 ±0.25 ±2.5 µA VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.6 3.6 3.6 3.6 4.0 0.002 TA = +25°C Typ 1.5 1.5 2.99 2.0 0.8 2.9 2.58 0.1 0.36 ±0.1 TA = −40°C to +85°C Guaranteed Limits 2.0 0.8 2.9 2.48 0.1 0.44 ±1.0 36 −25 40.0 V V V V V V µA mA mA µA VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 3.3 3.3 3.3 3.3 0.4 −0.4 1.6 1.6 0.8 −0.8 2.0 0.8 V V V V (Note 6)(Note 7) (Note 6)(Note 7) (Note 6)(Note 8) (Note 6)(Note 8) Units Conditions Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V. One output @ GND. Note 8: Max number of Data Inputs (n) switching. n−1 Inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 M Hz. www.fairchildsemi.com 2 74LVQ240 AC Electrical Characteristics TA = +25°C Symbol Parameter VCC (V) tPHL tPLH tPZL tPZH tPHZ tPLZ tOSHL tOSLH Output to Output Skew Data to Output (Note 9) Output Disable Time Propagation Delay Data to Output Output Enable Time 2.7 3.3 ± 0.3 2.7 3.3± 0.3 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 Min 2.0 2.0 2.5 2.5 1.0 1.0 CL = 50 pF Typ 8.4 7.0 9.6 8.0 10.2 8.5 1.0 1.0 Max 14.0 10.0 16.9 12.0 19.0 13.5 1.5 1.5 TA = −40°C to +85°C CL = 50 pF Min 2.0 2.0 2.5 2.5 1.0 1.0 Max 15.0 10.5 18.0 12.5 20.0 14.0 1.5 1.5 ns ns ns ns Units Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Symbol CIN CPD (Note 10) Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 70 Units pF pF VCC = Open VCC = 3.3V Conditions Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 74LVQ240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 4 74LVQ240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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