74LVT373

74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs September 1999 Revised March 2005 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state. The LVTH373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT373 and LVTH373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 373 s ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number 74LVT373WM 74LVT373SJ 74LVT373MTC 74LVTH373WM 74LVTH373SJ 74LVTH373MTC 74LVTH373MTCX_NL (Note 1) Package Number M20B M20D MTC20 M20B M20D MTC20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbols IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS012015 www.fairchildsemi.com 74LVT373 • 74LVTH373 Connection Diagram Pin Descriptions Pin Names D0–D7 LE OE O0–O7 Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs Truth Table Inputs LE X H H L H L Z X O0 Outputs Dn X L H X On Z L H O0 OE H L L L H IGH Voltage Level LOW Voltage Level High Impedance Immaterial Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description The LVT373 and LVTH373 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74LVT373 • 74LVTH373 Absolute Maximum Ratings(Note 2) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI  GND VO  GND VO ! VCC Output at HIGH State VO ! VCC Output at LOW State V V mA mA mA mA mA 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 64 128 r64 r128 65 to 150 qC Recommended Operating Conditions Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA 32 64 40 0 85 10 qC ns/V 't/'V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. 3 www.fairchildsemi.com 74LVT373 • 74LVTH373 DC Electrical Characteristics Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH ICCH ICCL ICCZ ICCZ Power Off Leakage Current Power up/down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 8) Note 4: All typical values are at VCC 3.3V, TA 25qC. Note 5: Applies to Bushold versions only (74LVTH373). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. TA Min 40qC to 85qC Typ (Note 4) Max Units V V V V V 0.2 0.5 0.4 0.5 0.55 V V V V V II Conditions 1.2 2.0 0.8 VCC  0.2 2.4 2.0 18 mA VO d 0.1V or VO t VCC  0.1V IOH IOH IOH IOL IOL IOL IOL IOL VI VI 100 PA 8 mA 32 mA 100 PA 24 mA 16 mA 32 mA 64 mA 0.8V 2.0V Bushold Input Minimum Drive 3.0 3.0 3.6 3.6 3.6 0 0–1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 75 PA PA PA PA 10 75 500 (Note 6) (Note 7) VI VI VI VI VO VI VO VO 5.5V 0V or VCC 0V VCC 0.5V to 3.0V GND or VCC 0.5V 3.0V 500 r1 5 1 PA PA PA PA PA PA PA PA PA mA mA mA mA mA r100 r100 5 5 10 0.19 5 0.19 0.19 0.2 0V d VI or VO d 5.5V VCC  V O d 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC d V O d 5.5V, Outputs Disabled One Input at VCC  0.6V Other Inputs at VCC or GND 'ICC Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 (Note 9) TA 25qC Typ 0.8 Max V V Units CL Conditions 50 pF, RL (Note 10) (Note 10) 500: Min 0.8 Note 9: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 4 74LVT373 • 74LVTH373 AC Electrical Characteristics TA CL Symbol Parameter Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tW tS tH LE Pulse Width Setup Time, Dn to LE Hold Time, Dn to LE 3.3V, T A 25qC. 40qC to 85qC 50 pF, RL 500: VCC Max 4.5 4.5 4.6 4.5 4.8 4.8 4.6 4.6 Min 1.5 1.5 1.7 1.7 1.3 1.3 1.9 1.9 3.0 1.0 1.4 2.7V Max 5.0 4.9 4.9 5.0 5.9 5.5 4.9 4.9 ns ns ns ns ns ns ns Units VCC 3.3V r0.3V Typ (Note 11) Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time 1.5 1.5 1.7 1.7 1.3 1.3 1.9 1.9 3.0 1.1 1.4 Note 11: All typical values are at VCC Capacitance (Note 12) Symbol CIN COUT Parameter Input Capacitance Output Capacitance VCC VCC OPEN, VI Conditions 0V or VCC 3.0V, VO 0V or VCC Typical 3 5 Units pF pF Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVT373 • 74LVTH373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74LVT373 • 74LVTH373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com