74LVTH125M

74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs January 2008 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs Features ■ Input and output interface capability to systems at ■ ■ ■ ■ ■ ■ ■ General Description The LVTH125 contains four independent non-inverting buffers with 3-STATE outputs. These buffers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH125 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. 5V VCC Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs source/sink –32mA/+64mA Functionally compatible with the 74 series 125 Latch-up performance exceeds 500mA ESD performance: – Human-body model > 2000V – Machine model > 200V – Charged-device model > 1000V Ordering Information Order Number 74LVTH125M 74LVTH125SJ 74LVTH125MTC Package Number M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names An, Bn On Description Inputs 3-STATE Outputs Truth Table Inputs An L L H Output Bn L H X On L H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 2 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VI VO Supply Voltage DC Input Voltage DC Output Voltage Output in 3-STATE Output in HIGH or LOW IIK IOK IO Parameter Rating –0.5V to +4.6V –0.5V to +7.0V –0.5V to +7.0V State(1) –0.5V to +7.0V –50mA –50mA 64mA 128mA ±64mA ±128mA –65°C to +150°C DC Input Diode Current, VI < GND DC Output Diode Current, VO < GND DC Output Current, VO > VCC Output at HIGH State Output at LOW State ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Note: 1. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI IOH IOL TA ∆t / ∆V Supply Voltage Input Voltage Parameter Min 2.7 0 Max 3.6 5.5 –32 64 Units V V mA mA °C ns/V HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V –40 0 85 10 ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 3 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs DC Electrical Characteristics TA = –40°C to +85°C Min. Symbol VIK VIH VIL VOH Typ.(2) Max. Units –1.2 V V 0.8 V V Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 Conditions II = –18mA VO ≤ 0.1V or VO ≥ VCC – 0.1V IOH = –100µA IOH = –8mA IOH = –32mA IOL = 100µA IOL = 24mA IOL = 16mA IOL = 32mA IOL = 64mA 2.0 VCC – 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 –75 500 –500 10 ±1 –5 1 ±100 ±100 –5 5 10 0.19 5 0.19 0.19 0.2 VOL Output LOW Voltage 2.7 3.0 V II(HOLD) II(OD) II Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins 3.0 3.0 3.6 3.6 3.6 0 0–1.5 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 VI = 0.8V VI = (3) (4) µA µA µA 2.0V VI = 5.5V VI = 0V or VCC V I = 0V VI = VCC 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V, VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO ≤ 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC ≤ VO ≤ 5.5V, Outputs Disabled One Input at VCC – 0.6V, Other Inputs at VCC or GND IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ∆ICC Power Off Leakage Current Power up/down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current(5) µA µA µA µA µA mA mA mA mA mA Notes: 2. All typical values are at VCC = 3.3V, TA = 25°C. 3. An external driver must source at least the specified current to switch from LOW-to-HIGH. 4. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 5. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 4 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs Dynamic Switching Characteristics(6) Conditions Symbol VOLP VOLV TA = 25°C Min. Typ. 0.8 –0.8 Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) CL = 50 pF, RL = 500Ω 3.3 3.3 (7) Max. Units V V (7) Notes: 6. Characterized in SOIC package. Guaranteed parameter, but not tested. 7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = –40°C to +85°C, CL = 50pF, RL = 500Ω VCC = 3.3V ± 0.3V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL, tOSLH Output to Output Skew(9) Notes: 8. All typical values are at VCC = 3.3V, TA = 25°C. 9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Output Disable Time Output Enable Time VCC = 2.7V Min. 1.0 1.0 1.0 1.1 1.5 1.3 Parameter Propagation Delay, Data to Output Min. 1.0 1.0 1.0 1.1 1.5 1.3 Typ.(8) Max. 3.5 3.9 4.0 4.0 4.5 4.5 1.0 Max. 4.5 4.9 5.5 5.4 5.7 4.0 1.0 Units ns ns ns ns Capacitance(10) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF Note: 10. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012. ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 5 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs Physical Dimensions 8.75 8.50 7.62 14 8 B A 0.65 5.60 6.00 4.00 3.80 PIN ONE INDICATOR 1 7 1.70 1.27 1.27 (0.33) 0.51 0.35 0.25 M LAND PATTERN RECOMMENDATION CBA 1.75 MAX 1.50 1.25 0.25 0.10 C 0.10 C SEE DETAIL A 0.25 0.19 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) DETAIL A SCALE: 20:1 SEATING PLANE Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 6 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 7 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs Physical Dimensions (Continued) 0.43 TYP 0.65 1.65 0.45 6.10 12.00° TOP R0.09 min & BOTTOM A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 8 74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter® * FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® PDP-SPM™ Power220® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™ -3 SuperSOT™ -6 SuperSOT™ -8 SupreMOS™ SyncFET™ ® The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©1998 Fairchild Semiconductor Corporation 74LVTH125 Rev. 1.4.0 www.fairchildsemi.com 9