74LVTH162374MEX

74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs July 2007 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Features ■ Input and output interface capability to systems at 5V ■ ■ ■ ■ tm General Description The LVTH162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LVTH162374 is designed with equivalent 25Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH162374 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ ■ ■ ■ VCC Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power Up/Power Down high impedance provides glitch-free bus loading Outputs include equivalent series resistance of 25Ω to make external termination resistors unnecessary and reduce overshoot and undershoot Functionally compatible with the 74 series 16374 Latch-up performance exceeds 500mA ESD performance: – Human-body model > 2000V – Machine model > 200V – Charged-device model > 1000V Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Information Order Number 74LVTH162374GX(1) 74LVTH162374MEA 74LVTH162374MEX 74LVTH162374MTD 74LVTH162374MTX Package Number BGA54A (Preliminary) MS48A MS48A MTD48 MTD48 Pb-Free Yes Yes Yes Yes Yes Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Supplied As Tape and Reel Tubes Tape and Reel 48-Lead Thin Shrink Small Outline Package Tubes (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package Tape and Reel (TSSOP), JEDEC MO-153, 6.1mm Wide Notes: 1. BGA package available in Tape and Reel only. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Connection Diagrams Pin Assignments for SSOP and TSSOP FBGA Pin Assignments 1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 CP1 NC VCC GND GND GND VCC NC CP2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15 Logic Symbol Truth Tables Pin Assignment for FPGA Inputs CP1 OE1 L L L X L H Outputs I0–I7 H L X X O0–O7 H L Oo Z Inputs CP2 OE2 L L (Top Thru View) Outputs I8–I15 H L X X O8–O15 H L Oo Z L X L H Pin Description Pin Name OEn CPn I0–I15 O0–O15 NC Description Output Enable Input (Active LOW) Clock Pulse Input Inputs 3-STATE Outputs No Connect H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance Oo = Previous Oo before LOW-to-HIGH of CP ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 2 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Functional Description The LVTH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi-vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 3 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Conditions Value -0.5 to +4.6 -0.5 to +7.0 Units V V V mA mA mA mA mA °C Output in 3-STATE Output in HIGH or LOW VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State State(2) -0.5 to +7.0 -0.5 to +7.0 -50 -50 64 128 ±64 ±128 -65 to +150 Note: 2. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI IOH IOL TA ∆ t/ ∆ V Supply Voltage Input Voltage Parameter Min. 2.7 0 Max. 3.6 5.5 -12 12 Units V V mA mA °C ns/V HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V -40 0 85 10 ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 4 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs DC Electrical Characteristics TA = -40°C to +85°C Symbol VIK VIH VIL VOH VOL II(HOLD) II(OD) II Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins VCC (V) 2.7 2.7–3.6 2.7–3.6 2.7–3.6 3.0 2.7 3.0 3.0 3.0 3.6 Conditions II = -18mA VO ≤ 0.1V or VO ≥ VCC – 0.1V IOH = -100µA IOH = -12mA IOL = 100µA IOL = 12mA VI = 0.8V VI = 2.0V (3) (4) MIn. 2.0 Max. Units -1.2 0.8 V V V V 0.2 0.8 V µA µA 10 ±1 -5 1 ±100 ±100 -5 5 10 0.19 5 0.19 0.19 0.2 µA µA µA µA µA mA mA mA mA mA µA VCC – 0.2V 2.0 75 -75 500 -500 VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ∆ICC Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current(5) 0 0–1.5 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V, VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO ≤ 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC ≤ VO ≤ 5.5V, Outputs Disabled One Input at VCC – 0.6V Other Inputs at VCC or GND Notes: 3. An external driver must source at least the specified current to switch from LOW-to-HIGH. 4. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 5. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 5 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Dynamic Switching Characteristics(6) VCC (V) 3.3 3.3 Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Conditions CL = 50pF, RL = 500Ω (7) (7) TA = -40°C to +85°C Min. Typ. 0.8 -0.8 Max Units V V Note: 6. Characterized in SSOP package. Guaranteed parameter, but not tested. 7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = -40°C to +85°C, CL = 50pF, RL = 500Ω VCC = 3.3V ±0.3V Symbol fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH VCC = 2.7V Min. 150 2.0 1.6 1.8 1.2 1.9 2.0 2.0 0.1 3.0 Parameter Maximum Clock Frequency Propagation Delay, CP to On Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width Output to Output Skew(8) Min. 160 2.0 1.6 1.8 1.2 1.9 2.0 1.8 0.8 3.0 Max. 5.1 5.3 5.0 5.6 5.0 5.4 Max. 5.3 6.2 6.0 6.9 5.1 5.7 Units MHz ns ns ns ns ns ns 1.0 1.0 1.0 1.0 ns Note: 8. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance(9) Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Conditions VCC = OPEN, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typ. 4 8 Units pF pF Note: 9. Capcitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 6 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 7 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 8 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MDT48 ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 9 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I30 Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 www.fairchildsemi.com 10