74LVTH273MTCX_NL

74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear July 1999 Revised March 2005 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock (CP) and Clear (CLR) are common to all flip-flops. The state of each D-type input, one setup time before the positive clock transition, is transferred to the corresponding flip-flop’s output. The LVTH273 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH273 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold on the data inputs eliminate the need for external pull-up resistors to hold unused inputs s Outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 273 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number 74LVTH273WM 74LVTH273SJ 74LVTH273MTC 74LVTH273MTCX_NL (Note 1) Package Number M20B M20D MTC20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbols IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS500100 www.fairchildsemi.com 74LVTH273 Connection Diagram Pin Descriptions Pin Names D0–D7 CP CLR O0–O7 Description Data Inputs Clock Pulse Input Clear Outputs Truth Table Inputs Dn H L X X CP Outputs CLR H H H L On H L Oo L   X H or L H H IGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Transition Oo Previous Oo before HIGH-to-LOW of CP  Functional Description The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input signal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74LVTH273 Absolute Maximum Ratings(Note 2) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in HIGH or LOW State (Note 3) VI  GND VO  GND VO ! VCC VO ! VCC Output at HIGH State Output at LOW State V mA mA mA mA mA 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 50 50 64 128 r64 r128 65 to 150 qC Recommended Operating Conditions Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA 32 64 40 0 85 10 qC ns/V 't/'V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) II(OD) II Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF ICCH ICCL Power Off Leakage Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 7) Note 4: All typical values are at VCC 3.3V, TA 25qC. TA 40qC to 85qC Min Typ (Note 4) Max Units V V 0.8 VCC  0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 V V V II Conditions 1.2 2.0 18 mA VO d 0.1V or VO t VCC  0.1V IOH IOH IOH IOL IOL IOL IOL IOL VI VI 100 PA 8 mA 32 mA 100 PA 24 mA 16 mA 32 mA 64 mA 0.8V 2.0V 3.0 3.0 3.6 3.6 3.6 0 3.6 3.6 3.6 75 500 PA PA 10 (Note 5) (Note 6) VI VI VI VI 5.5V 0V or VCC 0V VCC 500 r1 5 1 PA PA PA PA PA mA mA mA r100 0.19 5 0.2 0V d VI or VO d 5.5V Outputs HIGH Outputs LOW One Input at VCC  0.6V Other Inputs at VCC or GND 'ICC 3 www.fairchildsemi.com 74LVTH273 DC Electrical Characteristics (Continued) Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 (Note 8) TA Min 2 5 qC Typ 0.8 Max Units V V Conditions CL 50 pF, RL (Note 9) (Note 9) 500: 0.8 Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA CL Symbol Parameter Min VCC 40qC to 85qC 50 pF, RL 500: VCC Min 2.7V Max Units 3.3V r 0.3V Typ (Note 10) Max fMAX tPLH tPHL tPHL tW tS Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CLR to On Pulse Duration Setup Time Data HIGH or LOW before CP CLR HIGH before CP 150 1.7 1.9 1.6 3.3 2.3 2.3 0 4.9 4.8 4.8 150 1.7 1.9 1.6 3.3 2.7 2.7 0 5.5 5.1 5.4 MHz ns ns ns ns ns tH Hold Time Data HIGH or LOW after CP 3.3V, TA 25qC. Note 10: All typical values are at VCC Capacitance Symbol CIN COUT (Note 11) Parameter Conditions VCC VCC 0V, VI 0V or VCC 0V or VCC 3.0V, VO Typical 3 6 Units pF pF Input Capacitance Output Capacitance Note 11: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 4 74LVTH273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVTH273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com