74LVTH373WM

74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs February 2008 74LVT373, 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs Features ■ Input and output interface capability to systems at ■ General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state. The LVTH373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT373 and LVTH373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ ■ ■ ■ ■ 5V VCC Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373) Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs source/sink –32 mA/+64 mA Functionally compatible with the 74 series 373 ESD performance: – Human-body model > 2000V – Machine model > 200V – Charged-device model > 1000V Ordering Information Order Number 74LVT373WM 74LVT373SJ 74LVT373MTC 74LVTH373WM 74LVTH373SJ 74LVTH373MTC Package Number M20B M20D MTC20 M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names D0–D7 LE OE O0–O7 Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs Truth Table Functional Description The LVT373 and LVTH373 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs LE X H H L Outputs Dn X L H X OE H L L L On Z L H O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 2 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 3 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VI VO Supply Voltage DC Input Voltage DC Output Voltage Output in 3-STATE Output in HIGH or LOW IIK IOK IO Parameter Rating –0.5V to +4.6V –0.5V to +7.0V –0.5V to +7.0V State(1) –0.5V to +7.0V –50mA –50mA 64mA 128mA ±64mA ±128mA –65°C to +150°C DC Input Diode Current, VI < GND DC Output Diode Current, VO < GND DC Output Current, VO > VCC Output at HIGH State Output at LOW State ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Note: 1. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI IOH IOL TA ∆t / ∆V Supply Voltage Input Voltage Parameter Min 2.7 0 Max 3.6 5.5 –32 64 Units V V mA mA °C ns/V HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V –40 0 85 10 ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 4 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs DC Electrical Characteristics T A =–40°C to +85°C Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 Conditions II = –18mA VO ≤ 0.1V or VO ≥ VCC – 0.1V IOH = –100µA IOH = –8mA IOH = –32mA IOL = 100µA IOL = 24mA IOL = 16mA IOL = 32mA IOL = 64mA Min. 2.0 Typ.(2) Max. Units –1.2 0.8 V V V V VCC–0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 –75 500 –500 10 ±1 –5 1 ±100 ±100 –5 5 10 0.19 5 0.19 0.19 0.2 VOL Output LOW Voltage 2.7 3.0 V II(HOLD) (3) Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins 3.0 3.0 3.6 3.6 3.6 0 0–1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 VI = 0.8V VI = 2.0V (4) (5) µA µA µA II(OD)(3) II VI = 5.5V VI = 0V or VCC V I = 0V VI = VCC 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V, VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO ≤ 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC ≤ VO ≤ 5.5V, Outputs Disabled One Input at VCC – 0.6V, Other Inputs at VCC or GND IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ∆ICC Power Off Leakage Current Power up/down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current(6) µA µA µA µA µA mA mA mA mA mA Notes: 2. All typical values are at VCC = 3.3V, TA = 25°C. 3. Applies to bushold versions only (74LVTH373). 4. An external driver must source at least the specified current to switch from LOW-to-HIGH. 5. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 6. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 5 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Dynamic Switching Characteristics(7) Conditions Symbol VOLP VOLV TA = 25°C Min. Typ. 0.8 –0.8 Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 CL = 50pF, RL = 500Ω (8) Max. Units V V (8) Notes: 7. Characterized in SOIC package. Guaranteed parameter, but not tested. 8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = –40°C to +85°C, CL = 50pF, RL = 500Ω VCC = 3.3V ±0.3V Symbol tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tW tS tH LE Pulse Width Setup Time, Dn to LE Hold Time, Dn to LE Output Disable Time VCC = 2.7V Min. 1.5 1.5 1.7 1.7 1.3 1.3 1.9 1.9 3.0 1.0 1.4 Parameter Propagation Delay, Dn to On Propagation Delay, LE to On Output Enable Time Min. 1.5 1.5 1.7 1.7 1.3 1.3 1.9 1.9 3.0 1.1 1.4 Typ.(9) Max. 4.5 4.5 4.6 4.5 4.8 4.8 4.6 4.6 Max. 5.0 4.9 4.9 5.0 5.9 5.5 4.9 4.9 Units ns ns ns ns ns ns ns Note: 9. All typical values are at VCC = 3.3V, TA = 25°C. Capacitance(10) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VCC = OPEN, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 3 5 Units pF pF Note: 10. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 6 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions 13.00 12.60 11.43 20 B 11 A 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 0.51 0.35 0.25 M 10 1.27 CBA 1.27 0.65 LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A C 0.33 0.20 0.10 C SEATING PLANE 0.75 0.25 (R0.10) (R0.10) 8° 0° X 45° 0.30 0.10 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE 0.25 1.27 0.40 (1.40) A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P1030X265-20L F) DRAWING FILENAME: MKT-M20BREV3 SEATING PLANE DETAIL A SCALE: 2:1 Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 7 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 8 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions (Continued) Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 9 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 www.fairchildsemi.com 10