74LVX161284AMTX

74LVX161284A Low Voltage IEEE 161284 Translating Transceiver June 1999 Revised June 2005 74LVX161284A Low Voltage IEEE 161284 Translating Transceiver General Description The LVX161284A contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard, with the exception of output slew rate, and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (r 14 mA) and are connected to a separate power supply pin (VCCcable) to allow these outputs to be driven by a higher supply voltage than the Aside. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCCcable supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1–A8/B1–B8 transceiver pins. Features s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals with the exception of output slew rate s Translation capability allows outputs on the cable side to interface with 5V signals s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s Inputs and outputs on cable side have internal pull-up resistors s Flow-through pin configuration allows easy interface between the “Peripheral and Host” s Replaces the function of two (2) 74ACT1284 devices Ordering Code Order Number 74LVX161284AMTD 74LVX161284AMTX Package Number MTD48 MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Connection Diagram Pin Descriptions Pin Names HD DIR A1–A8 B1–B8 A9–A13 Y9–Y13 A14–A17 C14–C17 PLHIN PLH HLHIN HLH Description High Drive Enable Input (Active HIGH) Direction Control Input Inputs or Outputs Inputs or Outputs Inputs Outputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output Host Logic HIGH Input Host Logic HIGH Output © 2005 Fairchild Semiconductor Corporation DS500204 www.fairchildsemi.com 74LVX161284A Logic Symbol Truth Table Inputs DIR L HD L B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode L H B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 H L A1–A8 Data to B1–B8 (Note 2) A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode H H A1–A8 Data to B1–B8 A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 Note 1: Y9–Y13 Open Drain Outputs Note 2: B1–B8 Open Drain Outputs Outputs Logic Diagram www.fairchildsemi.com 2 74LVX161284A Absolute Maximum Ratings(Note 3) Supply Voltage VCC VCC—Cable VCC—Cable Must Be t VCC Input Voltage (VI)—(Note 4) A1–A13, PLHIN , DIR, HD B1–B8, C14–C17, HLHIN B1–B8, C14–C17, HLHIN Output Voltage (VO) A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH B1–B8, Y9–Y13, PLH DC Output Current (IO) A1–A8, HLH B1–B8, Y9–Y13 PLH (Output LOW) PLH (Output HIGH) Input Diode Current (IIK)—(Note 4) DIR, HD, A9–A13, PLH, HLH, C14–C17 Output Diode Current (IOK) A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH DC Continuous VCC or Ground Current Storage Temperature ESD (HBM) Last Passing Voltage Recommended Operating Conditions Supply Voltage VCC VCC—Cable DC Input Voltage (VI) Open Drain Voltage (VO) Operating Temperature (TA) 3.0V to 3.6V 3.0V to 5.5V 0V to VCC 0V to 5.5V 0.5V to 4.6V 0.5V to 7.0V 0.5V to VCC  0.5V 0.5V to 5.5V (DC) 2.0V to 7.0V* *40 ns Transient 40qC to 85qC 0.5V to VCC 0.5V 0.5V to 5.5V (DC) 2.0V to 7.0V* *40 ns Transient r25 mA r50 mA 84 mA 50 mA 20 mA r50 mA 50 mA r200 mA 65qC to 150qC 2000V Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIK VIH Input Clamp Diode Voltage Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN VOH Minimum HIGH Level Output Voltage Bn, Yn Bn, Yn PLH An, HLH Parameter VCC (V) 3.0 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.3 3.3 3.3 3.0 3.0 3.0 3.0 3.15 VCC—Cable TA (V) 3.0 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 5.0 5.0 5.0 3.0 3.0 3.0 4.5 3.15 40qC to 85qC Guaranteed Limits Units V Ii Conditions 1.2 2.0 2.3 2.6 0.8 0.8 1.6 0.4 0.8 0.2 2.8 2.4 2.0 2.23 3.1 18 mA V V VT–VT 'VT Minimum Input Hysteresis V VT–VT VT–VT IOH IOH 50 PA 4 mA 14 mA 14 mA 500 PA V IOH IOH IOH 3 www.fairchildsemi.com 74LVX161284A DC Electrical Characteristics Symbol VOL Maximum LOW Level Output Voltage Bn, Yn Bn, Yn PLH PLH RD Maximum Output Impedance Minimum Output Impedance RP Maximum Pull-Up Resistance Minimum Pull-Up Resistance IIH Maximum Input Current in HIGH State IIL Maximum Input Current in LOW State IOZH Maximum Output Disable Current (HIGH) IOZL Maximum Output Disable Current (LOW) IOFF IOFF IOFF—ICC IOFF—ICC2 ICC Power Down Output Leakage Power Down Input Leakage PowerDown Leakage to VCC Power Down Leakage to VCC—Cable Maximum Supply Current B1–B8, Y9–Y13, C14–C17 B1–B8, Y9–Y13 C14–C17 A9–A13, PLHIN, HD, DIR, HLHIN C14–C17 C14–C17 A9–A13, PLHIN, HD, DIR, HLHIN C14–C17 C14–C17 A1–A8 B1–B8 B1–B8 A1–A8 B1–B8 B1–B8 B1–B8, Y9–Y13, PLH C14–C17, HLHIN B1–B8, Y9–Y13 B1–B8, Y9–Y13 Parameter An, HLH (Continued) VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.0 0.0 0.0 0.0 3.6 3.6 VCC—Cable TA (V) 3.0 3.0 3.0 4.5 3.0 4.5 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.6 3.6 5.5 3.6 3.6 5.5 3.6 3.6 5.5 3.6 3.6 5.5 0.0 0.0 0.0 0.0 3.6 5.5 HIGH). 40qC to 85qC 0.2 0.4 0.8 0.77 0.95 0.9 60 55 30 35 1650 1650 1150 1150 1.0 50.0 100 Units IOL IOL V IOL IOL IOL IOL Conditions 50 PA 4 mA 14 mA 14 mA 84 mA 84 mA Guaranteed Limits (Note 5)(Note 7) : (Note 5)(Note 7) : VI 3.6V 3.6V 5.5V 0.0V 0.0V 0.0V 3.6V 3.6V 5.5V 0.0V PA VI VI 1.0 3.5 5.0 20 50 100 PA mA mA VI VI VI VO VO VO VO PA PA PA PA mA mA 20 3.5 5.0 100 100 250 250 45 70 PA PA PA PA mA VO VI 5.5V 5.5V (Note 6) (Note 6) VI VI VCC or GND VCC or GND Note 5: Output impedance is measured with the output active LOW and active HIGH (HD Note 6: Power-down leakage to V CC or VCC—Cable is tested by simultaneously forcing all pins on the cable-side (B1–B8, Y9–Y13, PLH, C14–C17 and HLHIN) to 5.5V and measuring the resulting ICC or ICC—Cable. Note 7: This parameter is guaranteed but not tested, characterized only. www.fairchildsemi.com 4 74LVX161284A AC Electrical Characteristics TA Symbol Parameter Min tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tSKEW tPHL tPLH tPHL tPLH tPHZ tPLZ tPZH tPZL tPHZ tPLZ tpEN tpDIS A1–A8 to B1–B8 A1–A8 to B1–B8 B1–B8 to A1–A8 B1–B8 to A1–A8 A9–A13 to Y9–Y13 A9–A13 to Y9–Y13 C14–C17 to A14–A 17 C14–C17 to A14–A 17 LH-LH or HL-HL PLHIN to PLH PLHIN to PLH HLHIN to HLH HLHIN to HLH Output Disable Time DIR to A1–A8 Output Enable Time DIR to A1–A8 Output Disable Time DIR to B1–B8 Output Enable Time HD to B1–B8, Y9–Y13 Output Disable Time HD to B1–B8, Y9–Y13 (i) A1–A8 to B1–B8, A9–A13 to Y9–Y13 (ii) B1–B8 to A1–A8 (iii) C14–C17 to A14–A17 40qC to  85qC 3.0V–3.6V 4.5V–5.5V Max 8.5 8.5 14.0 14.0 8.5 8.5 10.0 10.0 2.0 8.5 8.5 10.0 12.0 10.0 10.0 10.0 10.0 13.0 10.0 8.0 12.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 3 Figure 3 Figure 1 Figure 2 Figure 3 Figure 3 (Note 8) Figure 1 Figure 2 Figure 3 Figure 3 Figure 4 Figure 5 Figure 6 Figure 2 Figure 2 Units Figure Number VCC VCC—Cable 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Note 8: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type: Capacitance Symbol CIN CI/O (Note 9) Parameter Input Capacitance I/O Pin Capacitance Typ 3 5 Units pF pF VCC VCC 3.3V Conditions 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN) Note 9: CI/O is measured at frequency 1 MHz, per MIL-STD-883B, Method 3012 5 www.fairchildsemi.com 74LVX161284A AC Loading and Waveforms Pulse Generator for all pulses: Rate d1.0 MHz; ZO d 50:; tf d 2.5 ns, tr d 2.5 ns. FIGURE 1. Port A to B and A to Y Propagation Delay Waveforms FIGURE 2. Port A to B and A to Y Output Waveforms FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms www.fairchildsemi.com 6 74LVX161284A AC Loading and Waveforms (Continued) FIGURE 4. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8 FIGURE 5. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8 7 www.fairchildsemi.com 74LVX161284A AC Loading and Waveforms (Continued) FIGURE 6. tPHZ and tPLZ Test Load and Waveforms, DIR to B1–B8 www.fairchildsemi.com 8 74LVX161284A Low Voltage IEEE 161284 Translating Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com