74LVX74

74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop May 1993 Revised February 2005 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features s Input voltage level translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number 74LVX74M 74LVX74SJ 74LVX74MTC 74LVX74MTCX_NL (Note 1) Package Number M14A M14D MTC14 MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Pin Descriptions Pin Names D1 , D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs © 2005 Fairchild Semiconductor Corporation DS011606 www.fairchildsemi.com 74LVX74 Logic Symbols IEEE/IEC Truth Table (Each Half) Inputs SD L H L H H H CD H L L H H H CP X X D X X X H L X Q H L H H L Q0 Outputs Q L H H L H Q0   L X H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Clock Transition Q0(Q0) Previous Q(Q) before LOW-to-HIGH Transition of Clock  www.fairchildsemi.com 2 74LVX74 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC ) DC Input Diode Current (IIK) VI 0.5V to 7.0V 20 mA 0.5V to 7V 20 mA 20 mA 0.5V to VCC  0.5V r25 mA r50 mA 65qC to 150qC 180 mW Recommended Operating Conditions (Note 3) Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Input Rise and Fall Time ('t/'V) 2.0V to 3.6V 0V to 5.5V 0V to VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO 40qC to 85qC 0 ns/V to 100 ns/V 0.5V VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) Power Dissipation Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IIN ICC Input Leakage Current Quiescent Supply Current VCC 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 3.6 3.6 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 2.0 3.0 TA Min 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.48 0.1 0.1 0.44 V VIN VIL or VIH V 25qC Typ Max TA 40qC to 85qC Min 1.5 2.0 2.4 0.5 0.8 0.8 Max Units Conditions V V VIN VIL or VIH IOH IOH IOH IOL IOL IOL VIN VIN 5.5V or GND VCC or GND 50 PA 50 PA 4 mA 50 PA 50 PA 4 mA r0.1 2.0 r1.0 20.0 PA PA Noise Characteristics (Note 4) Symbol VOLP VOLV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage tf 3 ns VCC (V) 3.3 3.3 3.3 3.3 TA Typ 0.3 2 5 qC Limit 0.5 Units V V V V CL (pF) 50 50 50 50 0.3 0.5 2.0 0.8 Note 4: Input tr 3 www.fairchildsemi.com 74LVX74 AC Electrical Characteristics Symbol tPLH tPHL Parameter Propagation Delay CPn to Qn or Qn 3.3 r 0.3 tPLH tPHL Propagation Delay CDn to SDn to Qn or Qn 3.3 r 0.3 2.7 VCC (V) 2.7 Min TA 25qC Typ 7.3 9.8 5.7 8.2 8.4 10.9 6.6 9.1 Max 15 18.5 9.7 13.2 15.6 19.1 10.1 13.6 TA 40qC to 85qC Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 10 7 9.5 6.5 0.5 0.5 7.5 5.0 Max 18.5 22 11.5 15 18.5 22 12 15.5 Units CL (pF) 15 ns 50 15 50 15 50 15 50 ns tW tS tH tREC fMAX CPn or CDn or SDn Pulse Width Setup Time Dn to CPn Hold Time Dn to CPn Recovery Time CPn or SDn to CPn Maximum Clock Frequency 2.7 3.3 r 0.3 2.7 3.3 r 0.3 2.7 3.3 r 0.3 2.7 3.3 r 0.3 2.7 3.3 r 0.3 8.5 6 8.0 5.5 0.5 0.5 6.5 5.0 55 45 95 60 135 60 145 85 1.5 1.5 |tPHLm–tPHLn| ns ns ns ns 15 MHz 50 15 50 1.5 1.5 ns 50 50 40 80 50 tOSLH tOSHL Output to Output Skew (Note 5) 2.7 3.3 |tPLHm–tPLHn|, tOSLH Note 5: Parameter guaranteed by design. tOSLH Capacitance Symbol CIN CPD Input Capacitance Power Dissipation Capacitance (Note 6) Note 6: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Parameter Min TA 25qC Typ 4 25 Max 10 TA 40qC to 85qC Min Max 10 Units pF pF www.fairchildsemi.com 4 74LVX74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74LVX74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com