74LVXC3245

74LVXC3245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs February 1994 Revised October 2003 74LVXC3245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs General Description The LVXC3245 is a 24-pin dual-supply, 8-bit configurable voltage interface transceiver suited for PCMCIA and other real time configurable I/O applications. The VCCA pin accepts a 3V supply level. The A Port is a dedicated 3V port. The VCCB pin accepts a 3V-to-5V supply level. The B Port is configured to track the VCCB supply level respectively. A 5V level on the VCC pin will configure the I/O pins at a 5V level and a 3V VCC will configure the I/O pins at a 3V level. The A Port should interface with a 3V host system and the B Port to the card slots. This device will allow the VCCB voltage source pin and I/O pins on the B Port to float when OE is HIGH. This feature is necessary to buffer data to and from a PCMCIA socket that permits PCMCIA cards to be inserted and removed during normal operation. Features s Bidirectional interface between 3V and 3V-to-5V buses s Control inputs compatible with TTL level s Outputs source/sink up to 24 mA s Guaranteed simultaneous switching noise level and dynamic threshold performance s Implements patented EMI reduction circuitry s Flexible VCCB operating range s Allows B Port and VCCB to float simultaneously when OE is HIGH s Functionally compatible with the 74 series 245 Ordering Code: Order Number 74LVXC3245WM 74LVXC3245QSC 74LVXC3245MTC Package Number M24B MQA24 MTC24 Package Description 224-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names OE T/R A0–A7 B0–B7 Description Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs © 2003 Fairchild Semiconductor Corporation DS012008 www.fairchildsemi.com 74LVXC3245 Truth Table Inputs OE L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Outputs T/R L H X Bus B Data to Bus A Bus A Data to Bus B HIGH-Z State Logic Diagram www.fairchildsemi.com 2 74LVXC3245 Absolute Maximum Ratings(Note 1) Supply Voltage (VCCA, VCCB) DC Input Voltage (VI) @ OE, T/R DC Input/Output Voltage (VI/O) @ An @ Bn DC Input Diode Current (IIK) @ OE, T/R DC Output Diode (IOK) Current DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND ) and Max Current Storage Temperature Range (TSTG) DC Latch-Up Source or Sink Current −0.5V to +7.0V −0.5V to VCCA +0.5V −0.5V to VCCA +0.5V −0.5V to VCCB +0.5V ±20 mA ±50 mA ±50 mA ±50 mA ±200 mA −65°C to +150°C ±300 mA Recommended Operating Conditions (Note 2) Supply Voltage VCCA VCCB Input Voltage (VI) @ OE, T/R Input Output Voltage (VI/O) @ An @ Bn Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: The A Port unused pins (inputs or I/Os) must be held HIGH or LOW. They may not float. 2.7V to 3.6V 3.0V to 5.5V 0V to VCCA 0V to VCCA 0V to VCCB −40°C to +85°C 8 ns/V DC Electrical Characteristics Symbol VIHA Parameter Minimum HIGH Level Input Voltage VIHB An, OE T/R Bn VCCA (V) 2.7 3.0 3.6 2.7 3.0 3.6 VILA Maximum LOW Level Input Voltage VILB An, OE T/R Bn 2.7 3.0 3.6 2.7 3.0 3.6 VOHA Minimum HIGH Level Output Voltage 3.0 3.0 3.0 2.7 2.7 VOHB 3.0 3.0 3.0 3.0 VOLA Maximum LOW Level Output Voltage 3.0 3.0 2.7 2.7 VOLB 3.0 3.0 3.0 IIN Maximum Input Leakage Current @ OE, T/R 3.6 3.6 VCCB (V) 3.0 3.6 5.5 3.0 3.6 5.5 3.0 3.6 5.5 3.0 3.6 5.5 3.0 3.0 3.0 3.0 4.5 3.0 3.0 3.0 4.5 3.0 3.0 3.0 4.5 3.0 3.0 4.5 3.6 5.5 2.99 2.85 2.65 2.5 2.3 2.99 2.85 2.65 4.25 0.002 0.21 0.11 0.22 0.002 0.21 0.18 TA = 25°C Typ 2.0 2.0 2.0 2.0 2.0 3.85 0.8 0.8 0.8 0.8 0.8 1.65 2.9 2.56 2.35 2.3 2.1 2.9 2.56 2.35 3.86 0.1 0.36 0.36 0.42 0.1 0.36 0.36 ±0.1 ±0.1 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 2.0 2.0 2.0 3.85 0.8 0.8 0.8 0.8 0.8 1.65 2.9 2.46 2.25 2.2 2.0 2.9 2.46 2.25 3.76 0.1 0.44 0.44 0.5 0.1 0.44 0.44 ±1.0 ±1.0 µA V V V V IOUT = −100 µA IOH = −12 mA IOH = −24 mA IOH = −12 mA IOH = −24 mA IOUT = −100 µA IOH = −12 mA IOH = −24 mA IOH = −24 mA IOUT = 100 µA IOL = 24 mA IOL = 12 mA IOL = 24 mA IOUT = 100 µA IOL = 24 mA IOL = 24 mA VI = VCCA, GND V VOUT ≤ 0.1V or ≥VCC − 0.1V V Units Conditions VOUT ≤ 0.1V or ≥VCC − 0.1V 3 www.fairchildsemi.com 74LVXC3245 DC Electrical Characteristics Symbol IOZA Parameter Maximum 3-STATE Output Leakage @ An IOZB Maximum 3-STATE Output Leakage @ Bn ∆ICC ICCA1 Maximum ICC/Input Quiescent VCCA Supply Current as B Port Floats ICCA2 Quiescent VCCA Supply Current ICCB Quiescent VCCB Supply Current VOLPA VOLPB VOLVA VOLVB VIHDA VIHDB VILDA VILDB Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 3.6 3.6 3.6 3.6 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Note 3: Worst case package. (Continued) TA = 25°C Typ ±0.5 ±0.5 ±0.5 ±0.5 1.0 1.35 0.35 5 TA = −40°C to +85°C Guaranteed Limits ±5.0 ±5.0 ±5.0 ±5.0 1.5 0.5 50 µA µA VI = VIL, VIH, OE = VCCA VO = VCCA, GND VI = VIL, VIH, OE = VCCA VO = VCCB, GND VI = VCCB–2.1V VI = VCC–0.6V An = VCCA or GND Bn = Open, OE = VCCA, T/R = VCCA, VCCB = Open VCCA (V) 3.6 3.6 3.6 3.6 VCCB (V) 3.6 5.5 3.6 5.5 5.5 3.6 Open Units Conditions Bn All Inputs 3.6 3.6 3.6 mA µA 3.6 5.5 3.6 5.5 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5 5 5 8 0.8 0.8 0.8 1.5 −0.8 −0.8 −0.8 −1.2 2.0 2.0 2.0 3.5 0.8 0.8 0.8 1.5 50 50 50 80 µA µA An = VCCA or GND, Bn = VCCB or GND, OE = GND, T/R = GND An = VCCA or GND, Bn = VCCB or GND, OE = GND, T/R = VCCA V V V V V V V V (Note 3)(Note 4) (Note 3)(Note 4) (Note 3)(Note 4) (Note 3)(Note 4) (Note 3)(Note 5) (Note 3)(Note 5) (Note 3)(Note 5) (Note 3)(Note 5) Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. Note 5: Max number of Data Inputs (n) switching. (n–1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 M Hz. www.fairchildsemi.com 4 74LVXC3245 AC Electrical Characteristics TA = +25°C CL = 50 pF Symbol Parameter VCCA = 2.7V–3.6V VCCB = 4.5V–5.5V Min tPHL tPLH tPHL tPLH tPZL tPZH tPZL tPZH tPHZ tPLZ tPHZ tPLZ tOSHL tOSLH Propagation Delay A to B Propagation Delay B to A Output Enable Time OE to B Output Enable Time OE to A Output Disable Time OE to B Output Disable Time OE to A Output to Output Skew (Note 8) Data to Output Note 6: Typical values at VCCA = 3.3V, VCCB = 5.0V @ 25°C. Note 7: Typical values at VCCA = 3.3V, VCCB = 3.3V @ 25°C. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. TA = −40°C to +85°C CL = 50 pF VCCA = 2.7V–3.6V VCCB = 4.5V–5.5V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 8.5 7.0 7.0 8.0 8.5 9.0 10.0 9.5 8.5 8.0 10.0 7.0 1.5 TA = +25°C CL = 50 pF VCCA = 2.7V–3.6V VCCB = 3.0V–3.6V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ (Note 7) 5.5 5.2 4.4 5.1 6.0 6.1 6.4 5.8 6.3 4.5 5.2 3.4 1.0 Max 8.5 8.0 7.0 7.5 9.0 9.5 10.0 9.0 9.5 8.0 9.5 6.5 1.5 TA = −40°C to +85°C CL = 50 pF VCCA = 2.7V–3.6V VCCB = 3.0V–3.6V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 9.0 8.5 7.5 8.0 9.5 10.0 10.5 9.5 10.0 8.5 10.0 7.0 1.5 Units Typ (Note 6) 4.8 3.9 3.8 4.3 4.7 4.8 5.9 5.4 4.0 3.8 4.6 3.1 1.0 Max 8.0 6.5 6.5 7.5 8.0 8.5 9.5 9.0 8.0 7.5 9.5 6.5 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ns ns ns ns ns ns ns Capacitance Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (Note 9) Note 9: CPD is measured at 10 MHz. Parameter Typ 4.5 10 A→B B→A 50 40 Units pF pF pF pF VCC = Open VCCA = 3.3V VCCB = 5.0V VCCB = 5.0V VCCA = 3.3V Conditions 5 www.fairchildsemi.com 74LVXC3245 Power Up Considerations To insure the system does not experience unnecessary ICC current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to Table 1): • Power up the control side of the device first. This is the VCCA side. • OE should ramp with or ahead of VCCA. This will help guard against bus contention. • The Transmit/Receive control pin (T/R) should ramp with VCCA, this will ensure that the A Port data pins are configured as inputs. With VCCA receiving power first, the A I/O Port should be configured as inputs to help guard against bus contention and oscillations. • A side data inputs should be driven to a valid logic level. This will prevent excessive current draw. The above steps will ensure that no bus contention or oscillations, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the translator devices and potential damage to other system components. TABLE 1. Low Voltage Translator Power Up Sequencing Table Device Type 74LVXC3245 VCCA 3V (power up 1st) VCCB 3V to 5.5V configurable T/R ramp with VCCA OE ramp with VCCA A Side I/O logic 0V or VCCA B Side I/O outputs Floatable Pin Allowed yes, VCCB and B I/O’s w/ OE HIGH Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual Supply CMOS Translating Transceivers. Configurable I/O Application for PCMCIA Cards Block Diagram The LVXC3245 is a 24-pin dual supply device well suited for PCMCIA configurable I/O applications. Ideal for low power notebook designs, the LVXC3245 consumes less than 1 mW of quiescent power in all modes of operation. The LVXC3245 meets all PCMCIA I/O voltage requirements at 5V and 3.3V operation. By tying VCCB of the LVXC3245 to the card voltage supply, the PCMCIA card will always experience rail to rail output swings, maximizing the reliability of the interface. The VCCA pin on the LVXC3245 must always be tied to a 3V power supply. This voltage connection provides internal references needed to account for variations in VCCB. When connected as in the figure above, the LVXC3245 meets all the voltage and current requirements of the ISA bus standard (IEEE P996). www.fairchildsemi.com 6 74LVXC3245 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA24 7 www.fairchildsemi.com 74LVXC3245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com