74VHC02_07

74VHC02 — Quad 2-Input NOR Gate December 2007 74VHC02 Quad 2-Input NOR Gate Features ■ High Speed: tPD = 3.6ns (Typ.) at VCC = 5V ■ Low power dissipation: ICC = 2µA (Max.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (Max.) ■ Pin and function compatible with 74HC02 General Description The VHC02 is an advanced high-speed CMOS 2-Input NOR Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages, including buffer output, which provide high noise immunity and stable output. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC02M 74VHC02SJ 74VHC02MTC Package Number M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 74VHC02 — Quad 2-Input NOR Gate Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names An, Bn On Inputs Outputs Description Truth Table A L L H H B L H L H O H L L L ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 2 74VHC02 — Quad 2-Input NOR Gate Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC / GND Current Storage Temperature Parameter Rating –0.5V to +7.0V –0.5V to +7.0V –0.5V to VCC + 0.5V –20mA ±20mA ±25mA ±50mA –65°C to +150°C 260°C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR tr , tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time, VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 3 74VHC02 — Quad 2-Input NOR Gate DC Electrical Characteristics TA = 25°C Symbol VIH VIL VOH TA = –40°C to +85°C Max. Min. 1.50 0.7 x VCC 0.50 0.3 x VCC 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0–5.5 2.0 3.0–5.5 2.0 3.0 4.5 3.0 4.5 Conditions Min. 1.50 0.7 x VCC Typ. Max. Units V VIN = VIH or VIL IOH = –50µA 1.9 2.9 4.4 2.0 3.0 4.5 IOH = –4mA IOH = –8mA VIN = VIH or VIL IOL = 50µA 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 ±0.1 2.0 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 0.1 0.1 0.1 0.44 0.44 ±1.0 20.0 V IOL = 4mA IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND IIN ICC Input Leakage Current Quiescent Supply Current 0–5.5 5.5 µA µA Noise Characteristics TA = 25°C Symbol VOLP (2) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 Conditions CL = 50pF CL = 50pF CL = 50pF CL = 50pF Typ. 0.3 –0.3 Limits 0.8 –0.8 3.5 1.5 Units V V V V VOLV(2) VIHD(2) VILD(2) Note: 2. Parameter guaranteed by design. ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 4 74VHC02 — Quad 2-Input NOR Gate AC Electrical Characteristics TA = 25°C Symbol tPHL, tPLH TA = –40°C to +85°C Min. 1.0 1.0 1.0 1.0 Parameter Propagation Delay VCC (V) 3.3 ± 0.3 5.0 ± 0.5 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF VCC (3) = Open Min. Typ. 5.6 8.1 3.6 5.1 4 15 Max. 7.9 11.4 5.5 7.5 10 Max. 9.5 13.0 6.5 8.5 10 Units ns ns pF pF CIN CPD Input Capacitance Power Dissipation Capacitance Note: 3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per gate). ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 5 74VHC02 — Quad 2-Input NOR Gate Physical Dimensions 8.75 8.50 7.62 14 8 B A 0.65 5.60 6.00 4.00 3.80 PIN ONE INDICATOR 1 7 1.70 1.27 1.27 (0.33) 0.51 0.35 0.25 M LAND PATTERN RECOMMENDATION CBA 1.75 MAX 1.50 1.25 0.25 0.10 C 0.10 C SEE DETAIL A 0.25 0.19 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) DETAIL A SCALE: 20:1 SEATING PLANE Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 6 74VHC02 — Quad 2-Input NOR Gate Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 7 74VHC02 — Quad 2-Input NOR Gate Physical Dimensions (Continued) 0.43 TYP 0.65 1.65 0.45 6.10 12.00° TOP R0.09 min & BOTTOM A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 8 74VHC02 — Quad 2-Input NOR Gate TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® µSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©1992 Fairchild Semiconductor Corporation 74VHC02 Rev. 1.4.0 www.fairchildsemi.com 9