74VHC132M

74VHC132 Quad 2-Input NAND Schmitt Trigger May 2007 74VHC132 Quad 2-Input NAND Schmitt Trigger Features ■ High Speed: tPD = 3.9ns (Typ.) at VCC = 5V ■ Power down protection is provided on all inputs ■ Low power dissipation: ICC = 2µA (Max.) at TA = 25°C ■ Low noise: VOLP = 0.8V (Max.) ■ Pin and function compatible with 74HC132 tm General Description The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC00 but the inputs have hysteresis between the positive-going and negativegoing input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Thus greater noise margin then conventional gates is provided. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC132M 74VHC132MX_NL(1) 74VHC132SJ 74VHC132MTC 74VHC132MTCX_NL(1) Package Number M14A M14A M14D MTC14 MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Note: 1. Device available in Tape and Reel only. ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 74VHC132 Quad 2-Input NAND Schmitt Trigger Connection Diagram Logic Diagram Pin Description Pin Names An, Bn Yn Inputs Outputs Description Truth Table A L L H H B L H L H Y H H H L ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 2 74VHC132 Quad 2-Input NAND Schmitt Trigger Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC / GND Current Storage Temperature Parameter Rating –0.5V to +7.0V –0.5V to +7.0V –0.5V to VCC + 0.5V –20mA ±20mA ±25mA ±50mA –65°C to +150°C 260°C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(2) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR Supply Voltage Input Voltage Output Voltage Operating Temperature Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C Note: 2. Unused inputs must be held HIGH or LOW. They may not float. ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 3 74VHC132 Quad 2-Input NAND Schmitt Trigger DC Electrical Characteristics TA = 25°C Symbol VP TA = –40°C to +85°C Max. 2.20 3.15 3.85 Parameter Positive Threshold Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 2.0 3.0 4.5 3.0 4.5 Conditions Min. Typ. Min. Max. 2.20 3.15 3.85 Units V VN Negative Threshold Voltage 0.90 1.35 1.65 0.30 0.40 0.50 VIN = VIH or VIL IOH = –50µA 1.9 2.9 4.4 IOH = –4mA IOH = –8mA VIN = VIH or VIL IOL = 50µA 2.58 3.94 0.0 0.0 0.0 IOL = 4mA IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND 0.1 0.1 0.1 0.36 0.36 ±0.1 2.0 2.0 3.0 4.5 1.20 1.40 1.60 0.90 1.35 1.65 0.30 0.40 0.50 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 ±1.0 20.0 1.20 1.40 1.60 V VH Hysteresis Output Voltage V VOH HIGH Level Output Voltage V VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 V IIN ICC Input Leakage Current Quiescent Supply Current 0–5.5 5.5 µA µA Noise Characteristics TA = 25°C Symbol VOLP (3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Maximum Dynamic VOL Maximum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 Conditions CL = 50pF CL = 50pF CL = 50pF CL = 50pF Typ. 0.3 –0.3 Limits 0.8 –0.8 3.5 1.5 Units V V V V VOLV(3) VIHD(3) VILD(3) Note: 3. Parameter guaranteed by design. ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 4 74VHC132 Quad 2-Input NAND Schmitt Trigger AC Electrical Characteristics TA = 25°C Symbol Parameter VCC (V) 3.3 ± 0.3 5.0 ± 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance TA = –40°C to +85°C Max. 11.9 15.4 7.7 9.7 10 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF VCC (4) = Open Min. Typ. 6.1 8.0 3.9 5.9 4 16 Min. 1.0 1.0 1.0 1.0 Max. 14.0 17.5 9.0 11.0 10 Units ns tPHL, tPLH Propagation Delay pF pF Note: 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (Opr.) = CPD • VCC • IIN + ICC / 4 (per gate) ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 5 74VHC132 Quad 2-Input NAND Schmitt Trigger Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 6 74VHC132 Quad 2-Input NAND Schmitt Trigger Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 7 74VHC132 Quad 2-Input NAND Schmitt Trigger Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package MTC14 ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 8 74VHC132 Quad 2-Input NAND Schmitt Trigger TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ 2 E CMOS™ ® EcoSPARK EnSigna™ FACT Quiet Series™ ® FACT ® FAST FASTr™ FPS™ ® FRFET GlobalOptoisolator™ GTO™ HiSeC™ ® i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ Motion-SPM™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC ® OPTOPLANAR PACMAN™ PDP-SPM™ POP™ ® Power220 ® Power247 PowerEdge™ PowerSaver™ Power-SPM™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™ -3 SuperSOT™ -6 SuperSOT™ -8 SyncFET™ TCM™ ® The Power Franchise ™ TinyBoost™ TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ ® UHC UniFET™ VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I26 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1995 Fairchild Semiconductor Corporation 74VHC132 Rev. 1.4 www.fairchildsemi.com 9