74VHC273BQ

74VHC273 Octal D-Type Flip-Flop April 2007 74VHC273 Octal D-Type Flip-Flop Features ■ High Speed: fMAX = 165MHz (typ) at VCC = 5V ■ Low power dissipation: ICC = 4µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.9V (max) ■ Pin and function compatible with 74HC273 ■ Leadless DQFN Package tm General Description The VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The register has a common buffered Clock (CP) which is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The Master Reset (MR) input will clear all flip-flops simultaneously. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. An input protection circuit insures that 0V to 7V can be applied to the inputs pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC273M 74VHC273SJ 74VHC273BQ (Preliminary) 74VHC273MTC Package Number M20B M20D MLP020B (Preliminary) MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 74VHC273 Octal D-Type Flip-Flop Connection Diagrams Pin Assignments for PDIP, SOIC, SOP, and TSSOP Logic Symbols IEEE/IEC Pad Assignments for DQFN Function Table Operating Mode Reset (Clear) Load ‘1’ Load ‘0’ Inputs MR L H H Outputs Dn X H L CP X Qn L H L H = HIGH Voltage Level (Top Through View) L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Pin Descriptions Pin Names D0–D7 MR CP Q0–Q7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 2 74VHC273 Octal D-Type Flip-Flop Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 3 74VHC273 Octal D-Type Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC/GND Current Storage Temperature Parameter Rating –0.5V to +7.0V –0.5V to +7.0V –0.5V to VCC + 0.5V –20mA ±20mA ±25mA ±75mA –65°C to +150°C 260°C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR tr , tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time, VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 4 74VHC273 Octal D-Type Flip-Flop DC Electrical Characteristics TA = 25°C Symbol VIH VIL VOH –40°C to +85°C Max. Min. 1.50 0.7 x VCC 0.50 0.3 x VCC 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0–5.5 2.0 3.0–5.5 2.0 3.0 4.5 3.0 4.5 Conditions Min. 1.50 0.7 x VCC Typ. Max. Units V VIN = VIH IOH = –50µA or VIL IOH = –4mA IOH = –8mA VIN = VIH IOL = 50µA or VIL 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 ±0.1 4.0 0.1 0.1 0.1 0.44 0.44 ±1.0 40.0 V IOL = 4mA IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND IIN ICC Input Leakage Current Quiescent Supply Current 0–5.5 5.5 µA µA Noise Characteristics TA = 25°C Symbol VOLP(2) VOLV(2) VIHD(2) VILD(2) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 Conditions CL = 50pF CL = 50pF CL = 50pF CL = 50pF Typ. 0.6 –0.6 Limits 0.9 –0.9 3.5 1.5 Units V V V V Note: 2. Parameter guaranteed by design. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 5 74VHC273 Octal D-Type Flip-Flop AC Electrical Characteristics TA = 25°C Symbol fMAX TA = –40°C to +85°C Min. 65 45 100 70 13.6 17.1 9.0 11.0 13.6 17.1 8.5 10.5 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 16.0 19.5 10.5 12.5 16.0 19.5 10.0 12.0 1.5 1.0 10.0 pF pF ns ns ns ns ns MHz Parameter Maximum Clock Frequency VCC (V) 3.3 ± 0.3 5.0 ± 0.5 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF (3) Min. 75 50 120 80 Typ. 120 75 165 110 8.7 11.2 5.8 7.3 8.9 11.4 5.2 6.7 Max. Max. Units MHz tPLH, tPHL Propagation Delay Time (CK – Q) 3.3 ± 0.3 5.0 ± 0.5 tPHL Propagation Delay Time (MR – Q) 3.3 ± 0.3 5.0 ± 0.5 tOSLH, tOSHL CIN CPD Output to Output Skew Input Capacitance Power Dissipation Capacitance 3.3 ± 0.3 5.0 ± 0.5 CL = 50pF CL = 50pF = Open 4.0 31 VCC (4) 10.0 Notes: 3. Parameter guaranteed by design tOSLH = |tPLHmax – tPLHmin|; tOSHL = |tPHLmax – tPHLmin|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pieces of the Flip-Flop operates can be calculated by the equation: CPD (total) = 22 + 9n. AC Operating Requirements TA = 25°C Symbol tW(L), tW(H) tW(L) tS tH tREC TA = –40°C to +85°C Units ns ns ns ns ns 6.5 5.0 6.0 5.0 6.5 4.5 1.0 1.0 2.5 2.0 Parameter Minimum Pulse Width (CK) Minimum Pulse Width (MR) Minimum Setup Time Minimum Hold Time Minimum Removal Time (MR) VCC (V)(5) Typ. Guaranteed Minimum 5.5 5.0 5.0 5.0 5.5 4.5 1.0 1.0 2.5 2.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Note: 5. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 6 74VHC273 Octal D-Type Flip-Flop Tape and Reel Specification Tape Format for DQFN Package Designator BQ Tape Section Leader (Start End) Carrier Trailer (Hub End) Number Cavities 125 (typ.) 2500/3000 75 (typ.) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed Tape Dimensions Dimensions are in millimeters unless otherwise noted. Figure 2. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 7 74VHC273 Octal D-Type Flip-Flop Tape and Reel Specification (Continued) Reel Dimensions for DQFN Dimensions are in inches (millimeters) unless otherwise noted. Tape Size 12mm A 13.0 (330) B 0.059 (1.50) C 0.512 (13.00) D 0.795 (20.20) N 7.008 (178) W1 0.488 (12.4) W2 0.724 (18.4) Figure 3. ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 8 74VHC273 Octal D-Type Flip-Flop Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 9 74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 5. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 10 74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 6. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B (Preliminary) ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 11 74VHC273 Octal D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 12 74VHC273 Octal D-Type Flip-Flop TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1994 Fairchild Semiconductor Corporation 74VHC273 Rev. 1.5 www.fairchildsemi.com 13