74VHC374

74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs April 2007 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Features ■ High Speed: tPD = 5.4ns (typ) at VCC = 5V ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs ■ Low power dissipation: ICC = 4µA (Max) @ TA = 25°C ■ Pin and function compatible with 74HC374 tm General Description The VHC374 is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a HIGH impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC374M 74VHC374SJ 74VHC374MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names D0–D7 CP OE O0–O7 Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Logic Symbol IEEE/IEC Functional Description The VHC374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs Dn H L X X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition CP OE L L H Outputs On H L Z Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 2 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC/GND Current Storage Temperature Parameter Rating –0.5V to +7.0V –0.5V to +7.0V –0.5V to VCC + 0.5V –20mA ±20mA ±25mA ±75mA –65°C to +150°C 260°C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR tr , tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time, VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 3 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs DC Electrical Characteristics TA = 25°C Symbol VIH VIL VOH –40°C to +85°C Max. Min. 1.50 0.7 x VCC 0.50 0.3 x VCC 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0–5.5 2.0 3.0–5.5 2.0 3.0 4.5 3.0 4.5 Conditions Min. 1.50 0.7 x VCC Typ. Max. Units V VIN = VIH IOH = –50µA or VIL IOH = –4mA IOH = –8mA VIN = VIH IOL = 50µA or VIL 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 ±0.25 0.1 0.1 0.1 0.44 0.44 ±2.5 V IOL = 4mA IOL = 8mA VIN = VIH or VIL; VOUT = VCC or GND VIN = 5.5V or GND VIN = VCC or GND IOZ 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 5.5 µA IIN ICC 0–5.5 5.5 ±0.1 4.0 ±1.0 40.0 µA µA Noise Characteristics TA = 25°C Symbol VOLP (2) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 Conditions CL = 50pF CL = 50pF CL = 50pF CL = 50pF Typ. 0.6 –0.6 Limits 0.9 –0.9 3.5 1.5 Units V V V V VOLV(2) VIHD(2) VILD(2) Note: 2. Parameter guaranteed by design. ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 4 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs AC Electrical Characteristics TA = 25°C Symbol Parameter VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 RL = 1kΩ 5.0 ± 0.5 tPLZ, tPHZ 3-STATE Output Disable Time tOSLH, tOSHL fMAX Output to Output Skew Maximum Clock Frequency 3.3 ± 0.3 RL = 1kΩ 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance VCC = Open VCC (4) = 5.0V (3) TA = –40°C to +85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF Min. Typ. 8.1 10.6 5.4 6.9 7.1 9.6 5.1 6.6 10.2 6.1 Max. 12.7 16.2 8.1 10.1 11.0 14.5 7.6 9.6 14.0 8.8 1.5 1.0 Max. Units 15.0 18.5 9.5 11.5 13.0 16.5 9.0 11.0 16.0 10.0 1.5 1.0 ns MHz ns ns ns ns ns tPLH, tPHL Propagation Delay Time (CP to On) 80 55 130 85 130 85 185 120 4 6 32 10 70 50 110 75 10 pF pF pF Notes: 3. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min| 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) = 20 + 12n. AC Operating Requirements TA = 25°C Symbol tW(H), tW(L) tS tH TA = –40°C to +85°C Min. 5.5 5.0 4.5 3.0 2.0 2.0 ns ns Parameter Minimum Pulse Width (CP) Minimum Set-Up Time Minimum Hold Time VCC (V) 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 Min. 5.0 5.0 4.5 3.0 2.0 2.0 Typ. Max. Max. Units ns ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 5 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 2. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 6 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 7 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 8 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.com 9