74VHC573SJ

74VHC573 Octal D-Type Latch with 3-STATE Outputs May 2007 74VHC573 Octal D-Type Latch with 3-STATE Outputs Features ■ High Speed: tPD = 5.0ns (Typ.) at VCC = 5V ■ High Noise Immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power Down Protection is provided on all inputs ■ Low Noise: VOLP = 0.6V (Typ.) ■ Low Power Dissipation: ICC = 4µA (Max.) @ TA = 25°C ■ Pin and function compatible with 74HC573 tm General Description The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC573M 74VHC573SJ 74VHC573MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Description Pin Names D0–D7 LE OE O0–O7 Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Outputs ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 74VHC573 Octal D-Type Latch with 3-STATE Outputs Logic Symbol IEEE/IEC Functional Description The VHC573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches. Truth Table Inputs OE L L L H LE H H L X D H L X X Outputs On H L O0 Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 2 74VHC573 Octal D-Type Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC / GND Current Storage Temperature Parameter Rating –0.5V to +7.0V –0.5V to +7.0V –0.5V to VCC + 0.5V –20mA ±20mA ±25mA ±75mA –65°C to +150°C 260°C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR tr , tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time, VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 3 74VHC573 Octal D-Type Latch with 3-STATE Outputs DC Electrical Characteristics TA = 25°C Symbol VIH VIL VOH TA = –40°C to +85°C Max. Min. 1.50 0.7 x VCC 0.50 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0–5.5 2.0 3.0–5.5 2.0 3.0 4.5 3.0 4.5 Conditions Min. 1.50 0.7 x VCC Typ. Max. Units V 0.3 x VCC VIN = VIH IOH = –50µA or VIL 1.9 2.9 4.4 IOH = –4mA IOH = –8mA VIN = VIH IOL = 50µA or VIL 2.58 3.94 0.0 0.0 0.0 IOL = 4mA IOL = 8mA VIN = VIH or VIL, VOUT = VCC or GND VIN = 5.5V or GND VIN = VCC or GND 0.1 0.1 0.1 0.36 0.36 ±0.25 ±0.1 4.0 2.0 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 0.1 0.1 0.1 0.44 0.44 ±2.5 ±1.0 40.0 V IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 5.5 0–5.5 5.5 µA µA µA Noise Characteristics TA = 25°C Symbol VOLP (2) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 Conditions CL = 50pF CL = 50pF CL = 50pF CL = 50pF Typ. 0.9 –0.8 Limits 1.2 –1.0 3.5 1.5 Units V V V V VOLV(2) VIHD(2) VILD(2) Note: 2. Parameter guaranteed by design. ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 4 74VHC573 Octal D-Type Latch with 3-STATE Outputs AC Electrical Characteristics TA = 25°C Symbol tPLH, tPHL TA = –40°C to +85°C Max. 11.9 15.4 7.7 9.7 11.0 14.5 6.8 8.8 11.5 15.0 7.7 9.7 14.5 9.7 1.5 1.0 Parameter Propagation Delay Time (LE to On) VCC (V) 3.3 ± 0.3 5.0 ± 0.5 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF RL = 1kΩ CL = 15pF CL = 50pF CL = 15pF CL = 50pF RL = 1kΩ (3) Min. Typ. 7.6 10.1 5.0 6.5 7.0 9.5 4.5 6.0 7.3 9.8 5.2 6.7 10.7 6.7 Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 14.0 17.5 9.0 11.0 13.0 16.5 8.0 10.0 13.5 17.0 9.0 11.0 16.5 11.0 1.5 1.0 10 Units ns tPLH, tPHL Propagation Delay Time (D–On) 3.3 ± 0.3 5.0 ± 0.5 ns tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 5.0 ± 0.5 ns tPLZ, tPHZ 3-STATE Output Disable Time 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 CL = 50pF CL = 50pF CL = 50pF CL = 50pF ns ns pF pF pF tOSLH, tOSHL Output to Output Skew CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance VCC = Open VCC = 5.0V (4) 4 6 29 10 Notes: 3. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min| 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD • VCC • fIN + ICC / 8 (per Latch). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) = 21 + 8n. AC Operating Requirements VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tS tH Minimum Setup Time Minimum Hold Time 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 TA = 25°C Min. 5.0 5.0 3.5 3.5 1.5 1.5 TA = –40°C to +85°C Max. Min. 5.0 5.0 3.5 3.5 1.5 1.5 ns ns Symbol Parameter Typ. Max. Units ns tw(H), tw(L) Minimum Pulse Width (LE) ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 5 74VHC573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 6 74VHC573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 7 74VHC573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 8 74VHC573 Octal D-Type Latch with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ 2 E CMOS™ ® EcoSPARK EnSigna™ FACT Quiet Series™ ® FACT ® FAST FASTr™ FPS™ ® FRFET GlobalOptoisolator™ GTO™ ® HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ Motion-SPM™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC ® OPTOPLANAR PACMAN™ PDP-SPM™ POP™ ® Power220 ® Power247 PowerEdge™ PowerSaver™ Power-SPM™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ ® The Power Franchise ™ TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ ® UHC UniFET™ VCX™ Wire™ TinyBoost™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I27 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.com 9