74VHC574

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs March 1993 Revised May 2005 74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description The VHC574 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features s High Speed: tPD 5.6 ns (typ) at VCC VNIL 5V s High Noise Immunity: VNIH s Low Noise: VOLP 28% VCC (Min) s Power Down Protection is provided on all inputs 0.6V (typ) 4 PA (Max) @ TA 25qC s Low Power Dissipation: ICC s Pin and Function Compatible with 74HC574 Ordering Code: Order Number 74VHC574M 74VHC574SJ 74VHC574MTC 74VHC574N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Pin Names D0–D7 CP OE O0–O7 Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs © 2005 Fairchild Semiconductor Corporation DS011565 www.fairchildsemi.com 74VHC574 Functional Description The VHC574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Truth Table Inputs Dn H L X CP Outputs OE L L H On H L Z   X H H IGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74VHC574 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260qC 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC  0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Recommended Operating Conditions (Note 2) Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC VCC 3.3V r 0.3V 5.0V r 0.5V 0 a 100 ns/V 0 a 20 ns/V 2.0V to 5.5V 0V to 5.5V 0V to VCC 40qC to 85qC Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0  5.5 2.0 3.0  5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 5.5 4.0 40.0 0  5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 TA Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V IOL IOL VIN VOUT VIN VIN VIH or VIL VCC or GND 5.5V or GND VCC or GND 4 mA 8 mA V V VIN or VIL VIH IOH IOH IOL V 25qC Typ Max TA 40qC to 85qC Max Min 1.50 0.7 VCC Units V Conditions 0.50 0.3 VCC V VIN or VIL VIH IOH 50 PA 4 mA 8 mA 50 PA r0.25 r0.1 r2.5 r1.0 PA PA PA Noise Characteristics Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA Typ 1.0 25qC Limits 1.2 V V V V CL CL CL CL 50 pF 50 pF 50 pF 50 pF Units Conditions 0.8 1.0 3.5 1.5 Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC574 AC Electrical Characteristics Symbol tPLH tPHL Parameter Propagation Delay Time (CP to On) 5.0 r 0.5 tPZL tPZH 3-STATE Output Enable Time 5.0 r 0.5 tPLZ tPHZ tOSLH tOSHL fMAX 3-STATE Output Disable Time Output to Output Skew Maximum Clock Frequency 5.0 r 0.5 CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Note 4: Parameter guaranteed by design. tOSLH |tPLH max  t PLH min|; tOSHL |tPHL max  tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN  ICC/8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) 20  8n. VCC (V) 3.3 r 0.3 TA Min 2 5 qC Typ 8.5 11.0 5.6 7.1 8.2 10.7 5.9 7.4 11.0 7.1 Max 13.2 16.7 8.6 10.6 12.8 16.3 9.0 11.0 15.0 10.1 1.5 1.0 TA 40qC to 85qC Max 15.5 19.0 10.0 12.0 15.0 18.5 10.5 12.5 17.0 11.5 1.5 1.0 65 45 110 75 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Min Units ns ns ns ns ns ns RL RL Conditions CL CL CL CL 1 k: CL CL CL CL 1 k: CL CL (Note 4) CL CL CL CL CL CL VCC VCC Open 5.0V 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 50 pF 50 pF 50 pF 50 pF 15 pF 50 pF 15 pF 50 pF 3.3 r 0.3 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 80 50 130 85 125 75 180 115 4 6 28 10 MHz 10 pF pF pF (Note 5) AC Operating Requirements Symbol tW(H) tW(L) tS tH Minimum Set-Up Time Minimum Hold Time Parameter Minimum Pulse Width (CP) VCC (V) 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 TA Min 5.0 5.0 3.5 3.5 1.5 1.5 25qC Typ Max TA 40qC to 85qC Max Min 5.0 5.0 3.5 3.5 1.5 1.5 Units ns ns www.fairchildsemi.com 4 74VHC574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74VHC574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74VHC574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com