74VHCT374

74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs July 1997 Revised April 1999 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs General Description The VHCT374A is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flipflop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Note 1: Outputs in OFF-State. Features s High speed: fMAX = 140 MHz (typ) at TA = 25°C s High noise immunity: VIH = 2.0V, VIL = 0.8V s Power down protection is provided on all inputs and outputs s Low power dissipation: ICC = 4 µA (max) @ TA = 25°C s Pin and function compatible with 74HCT374 Ordering Code: Order Number 74VHCT374AM 74VHCT374ASJ 74VHCT374AMTC 74VHCT374AN Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Pin Names D0–D7 CP OE O0–O7 Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS500030.prf www.fairchildsemi.com 74VHCT374A Functional Description The VHCT374A consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Truth Table Inputs Dn H L X H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Outputs OE L L H On H L Z CP   X  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74VHCT374A Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) (Note 3) (Note 4) Input Diode Current (IIK) Output Diode Current (IOK) (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260°C ±20 mA ±25 mA ±75 mA −65°C to +150°C −0.5V to VCC + 0.5V −0.5V to +7.0V −20 mA −0.5V to +7.0V −0.5V to +7.0V Recommended Operating Conditions (Note 6) Supply Voltage (VCC) Input Voltage (VIN ) Output Voltage (VOUT) (Note 3) (Note 4) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: When outputs are in OFF-State or when VCC = OV. Note 5: VOUT < GND, V OUT > VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. 4.5V to +5.5V 0V to +5.5V 0V to VCC 0V to 5.5V −40°C to +85°C DC Electrical Characteristics Symbol VIH VIL VOH VOL IOZ IIN ICC ICCT IOFF Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage 3-STATE Output OFF-State Current Input Leakage Current Quiescent Supply Current Maximum ICC/Input Output Leakage Current (Power Down State) VCC (V) 4.5 5.5 4.5 5.5 4.5 4.5 5.5 0–5.5 5.5 5.5 0.0 4.40 3.94 0.0 0.1 0.36 ±0.25 ±0.1 4.0 1.35 0.5 4.50 TA = 25°C Min 2.0 2.0 0.8 0.8 4.40 3.80 0.1 0.44 ±2.5 ±1.0 40.0 1.50 5.0 Typ Max TA = −40°C to +85°C Min 2.0 2.0 0.8 0.8 Max Units V V V V V V µA µA µA mA µA VIN = VIH VIN = VIH IOH = −50 µA IOL = +50 uA Conditions or VIL IOH = −8 mA or VIL IOL = +8 mA VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5V or GND VIN = VCC or GND VIN = 3.4V Other Inputs = VCC or GND VOUT = 5.5V Noise Characteristics Symbol VOLP (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7) Note 7: Parameter guaranteed by design. Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA = 25°C Typ 1.2 −1.2 Limits 1.6 −1.6 2.0 0.8 Units V V V V Conditions CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF 3 www.fairchildsemi.com 74VHCT374A AC Electrical Characteristics Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ tOSLH tOSHL fMAX CIN COUT CPD Maximum Clock Frequency Input Capacitance Output Capacitance Power Dissipation Capacitance Output to Output Skew 3-STATE Output Disable Time 3-STATE Output Enable Time Parameter Propagation Delay Time VCC (V) 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 90 85 140 130 4 9 25 10 TA = 25°C Min Typ 4.1 5.6 6.5 7.3 7.0 Max 9.4 10.4 10.2 11.2 11.2 1.0 80 75 10 TA = −40°C to +85°C Min 1.0 1.0 1.0 1.0 1.0 Max 10.5 11.5 11.5 12.5 12.0 1.0 MHz pF pF pF Units ns ns ns Conditions CL = 15 pF CL = 50 pF RL = 1 kΩ CL = 15 pF CL = 50 pF RL = 1 kΩ CL = 50 pF (Note 8) CL = 15 pF CL = 50 pF VCC = Open VCC = 5.0V (Note 9) Note 8: Parameter guaranteed by design. tOSLH = |tPLH max − t PLH min|; tOSHL = |tPHL max − tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pcs. of the octal D Flip-Flop operates can be calculated by the equation: CPD(total) = 20 + 12m. AC Operating Requirements Symbol tW(H) tW(L) tS tH Parameter Minimum Pulse Width (CP) Minimum Set-up Time Minimum Hold Time VCC (V) 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 TA = 25°C Min 6.5 2.5 2.5 Typ Max TA = −40°C to +85°C Min 8.5 2.5 2.5 Max Units ns ns www.fairchildsemi.com 4 74VHCT374A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74VHCT374A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.