74VHCT74ASJ

74VHCT74A Dual D-Type Flip-Flop with Preset and Clear May 2007 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Features ■ High speed: fMAX = 160MHz (Typ.) at TA = 25°C ■ High noise immunity: VIH = 2.0V, VIL = 0.8V ■ Power down protection is provided on all inputs and tm General Description The VHCT74A is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to the Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC = 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. outputs Low power dissipation: ICC = 2µA (Max.) at TA = 25°C ■ ■ Pin and function compatible with 74HCT74 Ordering Information Order Number 74VHCT74AM 74VHCT74AMX_NL(1) 74VHCT74ASJ 74VHCT74AMTC 74VHCT74AMTCX_NL(1) Package Number M14A M14A M14D MTC14 MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Note: 1. Device available in Tape and Reel only. ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names D1, D2 CK1, CK2 CLR1, CLR2 PR1, PR2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Preset Inputs Outputs Truth Table Inputs CLR L H L H H H Outputs CK X X X PR H L L H H H D X X X L H X Q L H H L H Qn Q H L H H L Qn Function Clear Preset No Change ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 2 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT Supply Voltage DC Input Voltage DC Output Voltage Note 2 Note 3 IIK IOK IOUT ICC TSTG TL Input Diode Current Output Diode Current(4) DC Output Current DC VCC / GND Current Storage Temperature Parameter Rating –0.5V to +7.0V –0.5V to +7.0V –0.5V to VCC + 0.5V –0.5V to 7.0V –20mA ±20mA ±25mA ±50mA –65°C to +150°C 260°C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(5) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT Supply Voltage Input Voltage Output Voltage Note 2 Note 3 TOPR t r, t f Operating Temperature Input Rise and Fall Time VCC = 5.0V ±0.5V Parameter Rating 4.5V to +5.5V 0V to +5.5V 0V to VCC 0V to 5.5V –40°C to +85°C 0ns/V ∼ 20ns/V Notes: 2. HIGH or LOW state. IOUT absolute maximum rating must be observed. 3. VCC = 0V. 4. VOUT < GND, VOUT > VCC (Outputs Active). 5. Unused inputs must be held HIGH or LOW. They may not float. ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 3 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear DC Electrical Characteristics TA = 25°C Symbol VIH VIL VOH VOL IIN ICC ICCT IOFF TA = –40°C to +85°C Min. 2.0 2.0 0.8 0.8 0.8 0.8 4.40 3.80 0.1 0.36 ±0.1 2.0 1.35 +0.5 0.1 0.44 ±1.0 20.0 1.50 +5.0 µA µA mA µA V V V Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current Quiescent Supply Current Maximum ICC / Input Output Leakage Current (Power Down State) VCC (V) 4.5 5.5 4.5 5.5 4.5 4.5 4.5 4.5 0–5.5 5.5 5.5 0.0 Conditions Min. 2.0 2.0 Typ. Max. Max. Units V VIN = VIH IOH = –50µA or VIL IOH = –8mA VIN = VIH IOL = 50µA or VIL IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND VIN = 3.4V, Other Inputs = VCC or GND VOUT = 5.5V 4.40 3.94 4.50 0.0 AC Electrical Characteristics TA = 25°C Symbol fMAX TA = –40°C to +85°C Min. 80 65 7.8 8.8 10.4 11.4 10 1.0 1.0 1.0 1.0 9.0 10.0 12.0 13.0 10 pF pF ns ns Parameter Maximum Clock Frequency VCC (V)(6) 5.0 5.0 5.0 5.0 5.0 5.0 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF VCC (7) = Open Min. 100 80 Typ. 160 140 5.8 6.3 7.6 8.1 4 24 Max. Max. Units MHz tPLH, tPHL Propagation Delay Time (CK-Q, Q) tPLH, tPHL Propagation Delay Time (CLR, PR-Q, Q) CIN CPD Input Capacitance Power Dissipation Capacitance Notes: 6. VCC is 5.0 ± 0.5V 7. CPD is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD • VCC • fIN + ICC / 2 (per flip-flop). ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 4 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear AC Operating Requirements TA = 25°C Symbol tW(L), tW(H) tW(L) tS tH tREM TA = –40°C to +85°C Guaranteed Minimum Units ns ns ns ns ns Parameter Minimum Pulse Width (CK) Minimum Pulse Width (CLR, PR) Minimum Setup Time Minimum Hold Time Minimum Removal Time (CLR, PR) VCC (V) 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 Typ. 5.0 5.0 5.0 0 3.5 5.0 5.0 5.0 0 3.5 ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 5 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 6 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 7 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 8 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ 2 E CMOS™ ® EcoSPARK EnSigna™ FACT Quiet Series™ ® FACT ® FAST FASTr™ FPS™ ® FRFET GlobalOptoisolator™ GTO™ ® HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ Motion-SPM™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC ® OPTOPLANAR PACMAN™ PDP-SPM™ POP™ ® Power220 ® Power247 PowerEdge™ PowerSaver™ Power-SPM™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ ® The Power Franchise ™ TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ ® UHC UniFET™ VCX™ Wire™ TinyBoost™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I27 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1997 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.3 www.fairchildsemi.com 9