AN-4151

www.fairchildsemi.com Application Note AN-4151 Half-bridge LLC Resonant Converter Design Using FSFR-series Fairchild Power Switch (FPS™) Introduction The effort to obtain ever-increasing power density of switched-mode power supplies has been limited by the size of passive components. Operation at higher frequencies considerably reduces the size of passive components, such as transformers and filters; however, switching losses have been an obstacle to high-frequency operation. To reduce switching losses and allow high-frequency operation, resonant switching techniques have been developed. These techniques process power in a sinusoidal manner and the switching devices are softly commutated. Therefore, the switching losses and noise can be dramatically reduced [17]. Among various kinds of resonant converters, the simplest and most popular resonant converter is the LC series resonant converter, where the rectifier-load network is placed in series with the L-C resonant network, as depicted in Figure 1 [2-4]. In this configuration, the resonant network and the load act as a voltage divider. By changing the frequency of driving voltage Vd, the impedance of the resonant network changes. The input voltage is split between this impedance and the reflected load. Since it is a voltage divider, the DC gain of a LC series resonant converter is always 0 if sin(ωt ) < 0 (2) where Vo is the output voltage. The fundamental component of VRI is given as: VRI F = 4Vo π sin(ωt ) (3) Resonant network Rectifier network Ip + Vd Lr Im Cr Lm n:1 ID Io Ro + VO - Since harmonic components of VRI are not involved in the power transfer, AC equivalent load resistance can be calculated by dividing VRIF by Iac as: Vin Q2 Rac = VRI F 8V 8 = 2 o = 2 Ro I ac π Io π (4) - Considering the transformer turns ratio (n=Np/Ns), the equivalent load resistance shown in the primary side is obtained as: Figure 3. Schematic of Half-bridge LLC Resonant Converter © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 2 Rac = 8n 2 π 2 Ro (5) www.fairchildsemi.com AN4151 APPLICATION NOTE By using the equivalent load resistance, the AC equivalent circuit is obtained, as illustrated in Figure 6, where VdF and VROF are the fundamental components of the driving voltage, Vd and reflected output voltage, VRO (nVRI), respectively. I ac pk where: L p = Lm + Lr , Rac = Lr 1 , ωo = Q= Cr Rac 8n 2 π 2 Ro , m = Lp Lr 1 L p Cr 1 , ωp = Lr Cr Io Iac + VRI + Ro VO - As can be seen in Equation 6, there are two resonant frequencies. One is determined by Lr and Cr, while the other is determined by Lp and Cr. Equation 6 shows the gain is unity at resonant frequency (ωo), regardless of the load variation, which is given as: M= 2 2n ⋅ Vo (m − 1) ⋅ ω p = = 1 at ω = ωo (7) Vin ωo 2 − ω p 2 Iac VRIF VRI Vo I ac = π ⋅ Io 2 sin( wt ) VRI F = 4Vo π sin( wt ) Figure 5. Derivation of Equivalent Load Resistance Rac Vd + Cr Lr + Lm Np:Ns Vin VO Ro - + The gain of Equation 6 is plotted in Figure 7 for different Q values with m=3, fo=100kHz, and fp=57kHz. As observed in Figure 7, the LLC resonant converter shows gain characteristics that are almost independent of the load when the switching frequency is around the resonant frequency, fo. This is a distinct advantage of LLC-type resonant converter over the conventional series resonant converter. Therefore, it is natural to operate the converter around the resonant frequency to minimize the switching frequency variation. The operating range of the LLC resonant converter is limited by the peak gain (attainable maximum gain), which is indicated with ‘*’ in Figure 7. It should be noted that the peak voltage gain does not occur at fo nor fp. The peak gain frequency where the peak gain is obtained exists between fp and fo, as shown in Figure 7. As Q decreases (as load decreases), the peak gain frequency moves to fp and higher peak gain is obtained. Meanwhile, as Q increases (as load increases), the peak gain frequency moves to fo and the peak gain drops; thus, the full load condition should be the worst case for the resonant network design. fp = 2.0 VRI - n=Np/Ns Rac = 8n 2 π2 Ro Cr Lr Lm Rac V dF VRoF (nVRIF) Figure 6. AC Equivalent Circuit for LLC Resonant Converter 1 2π L p Cr fo = 1 2π Lr Cr Q=0.25 With the equivalent load resistance obtained in Equation 5, the characteristics of the LLC resonant converter can be derived. Using the AC equivalent circuit of Figure 6, the voltage gain, M, is obtained as: Gain ( 2nVo / Vin ) Q= 1.8 Lr / Cr Rac Q=1.0 Q=0.75 1.6 4n ⋅ Vo sin(ωt ) VRO F n ⋅ VRI F 2n ⋅ Vo M= F = =π = F 4 Vin Vd Vd Vin sin(ωt ) (6) π2 1.4 Q=0.50 Q=0.25 1.2 ω2 ) ( m − 1) ωo = ω2 ω ω2 ( 2 − 1) + j ( 2 − 1)(m − 1)Q ωp ωo ωo ( 1.0 Q=1.0 0.8 M @ fo = 1 0.6 40 50 60 70 80 90 freq (kHz) 100 110 120 130 140 Figure 7. Typical Gain Curves of LLC Resonant Converter (m=3) © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 3 AN4151 APPLICATION NOTE 2. Consideration for Integrated Transformer For practical design, it is common to implement the magnetic components (series inductor and shunt inductor) using an integrated transformer; where the leakage inductance is used as a series inductor, while the magnetizing inductor is used as a shunt inductor. When building the magnetizing components in this way, the equivalent circuit in Figure 6 should be modified as shown in Figure 8 because the leakage inductance exists, not only in the primary side, but also in the secondary side. Not considering the leakage inductance in the transformer secondary side generally results in an incorrect design. 2n ⋅ VO M= = Vin ω2 ) ⋅ (m − 1) ⋅ M V ωo ω2 ω ω2 ( 2 − 1) + j ( ) ⋅ ( 2 − 1) ⋅ (m − 1)Q e ωp ωo ωo ( ( (9) ω2 ) m( m − 1) ωo 2 = 2 ω ω ω2 ( 2 − 1) + j ( ) ⋅ ( 2 − 1) ⋅ ( m − 1) ⋅ Q e ωp ωo ωo where: Rac e = Qe = L 8n 2 Ro , m= p Lr π 2 MV 2 Lr 1 , ωo = Cr Rac e 1 , ωp = Lr Cr 1 L p Cr Vin Vd + Cr Llkp Llks + VO + The gain at the resonant frequency (ωo) is fixed regardless of the load variation, which is given as: Lm n:1 VRI Ro - M = MV = Lp Lp − Lr = m m −1 at ω = ωo (10) Lr = Llkp + Lm //(n 2 Llks ) = Llkp + Lm // Llkp L p = Llkp + Lm + Cr Lr Lp-Lr - 1: M V (M V = Lp L p − Lr ) ideal transformer + Vin F Rac VROF (nVRIF) - The gain at the resonant frequency (ωo) is unity when using individual core for series inductor, as shown in Equation 7. However, when implementing the magnetic components with integrated transformer, the gain at the resonant frequency (ωo) is larger than unity due to the virtual gain caused by the leakage inductance in the transformer secondary side. The gain of Equation 9 is plotted in Figure 10 for different Qe values with m=3, fo=100kHz, and fp=57kHz. As observed in Figure 9, the LLC resonant converter shows gain characteristics almost independent of the load when the switching frequency is around the resonant frequency, fo. fp = 2.2 Figure 8. Modified Equivalent Circuit to Accommodate the Secondary-side Leakage Inductance In Figure 8, the effective series inductor (Lp) and shunt inductor (Lp-Lr) are obtained by assuming n2Llks=Llkp and referring the secondary-side leakage inductance to the primary side as: 1 2π L p Cr fo = 1 2π Lr Cr Qe=0.25 Qe = Lr / Cr Rac e Qe=1.00 L p = Lm + Llkp Lr = Llkp + Lm //(n 2 Llks ) = Llkp + Lm // Llkp 2.0 (8) 1.8 Qe=0.75 Gain ( 2nVo / Vin ) 1.6 Qe=0.50 Qe=0.25 When handling an actual transformer, equivalent circuit with Lp and Lr is preferred since these values can be easily measured with a given transformer. In an actual transformer, Lp and Lr can be measured in the primary side with the secondary-side winding open circuited and short circuited, respectively. In Figure 9, notice that a virtual gain MV is introduced, which is caused by the secondary-side leakage inductance. By adjusting the gain equation of Equation 6 using the modified equivalent circuit of Figure 9, the gain equation for integrated transformer is obtained: 1.4 1.2 M @ fo = M V Qe=1.0 1.0 0.8 40 50 60 70 80 90 freq (kHz) 100 110 120 130 140 Figure 9. Typical Gain Curves of LLC Resonant Converter (m=3) Using an Integrated Transformer © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 4 AN4151 APPLICATION NOTE 3. Consideration of Operation Mode and Attainable Maximum Gain Operation Mode The LLC resonant converter can operate at frequency below or above the resonance frequency (fo), as illustrated in Figure 10. Figure 11 shows the waveforms of the currents in the transformer primary side and secondary side for each operation mode. Operation below the resonant frequency (case I) allows the soft commutation of the rectifier diodes in the secondary side, while the circulating current is relatively large. The circulating current increases more as the operation frequency moves downward from the resonant frequency. Meanwhile, operation above the resonant frequency (case II) allows the circulating current to be minimized, but the rectifier diodes are not softly commutated. Below resonance operation is preferred for high output voltage applications, such as Plasma Display Panel (PDP) TV where the reverse recovery loss in the rectifier diode is severe. Below resonance operation also has a narrow frequency range with respect to the load variation since the frequency is limited below the resonance frequency even at no load condition. Ip 1 2 fo Im 1 2 fS (I) fs < fo IDS1 ID IO Ip (II) fs > fo Im IDS1 ID IO Figure 11. Waveforms of Each Operation Mode On the other hand, above resonance operation has less conduction loss than the below resonance operation. It can show better efficiency for low output voltage applications, such as Liquid Crystal Display (LCD) TV or laptop adaptor, where Schottky diodes are available for the secondary-side rectifiers and reverse recovery problems are insignificant. However, operation at above the resonant frequency may cause too much frequency increase at lightload condition. Above frequency operation requires frequency skipping to prevent too much increase of the switching frequency. Required Maximum Gain and Peak Gain Above the peak gain frequency, the input impedance of the resonant network is inductive and the input current of the resonant network (Ip) lags the voltage applied to the resonant network (Vd). This permits the MOSFETs to turn on with zero voltage (ZVS), as illustrated in Figure 12. Meanwhile, the input impedance of the resonant network becomes capacitive and Ip leads Vd below the peak gain frequency. When operating in capacitive region, the MOSFET body diode is reverse recovered during the switching transition, which results in severe noise. Another problem of entering into the capacitive region is that the output voltage becomes out of control since the slope of the gain is reversed. The minimum switching frequency should be well limited above the peak gain frequency. Gain (M) B A Load increase M capacitive region peak gain inductive region I II Below resonance (fsfo) fs Vd Ip fo fs Vd Ip Figure 10. Operation Modes According to the Operation Frequency IDS1 reverse recovery IDS1 ZVS Figure 12. Operation Waveforms for Capacitive and Inductive Regions © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 5 AN4151 APPLICATION NOTE The available input voltage range of the LLC resonant converter is determined by the peak voltage gain. Thus, the resonant network should be designed so that the gain curve has an enough peak gain to cover the input voltage range. However, ZVS condition is lost below the peak gain point, as depicted in Figure 12. Therefore, some margin is required when determining the maximum gain to guarantee stable ZVS operation during the load transient and start-up. Typically 10~20% of the maximum gain is used as a margin for practical design, as shown in Figure 13. 2.2 2.1 2 1.9 1.8 1.7 peak gain 1.6 Gain (M) peak gain 10~20% of Mmax 1.5 m=2.25 1.4 m=2.5 maximum operation gain (Mmax) 1.3 m=3.0 1.2 1.1 m=6.0 m=9.0 m=8.0 m=7.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 m=3.5 m=4.0 m=4.5 m=5.0 1 0.9 1 1.1 1.2 1.3 1.4 Q fo Figure 13. Determining the Maximum Gain fs Figure 14. Peak Gain (Attainable Maximum Gain) vs. Q for Different m Values Even though the peak gain at a given condition can be obtained by using the gain in Equation 6, it is difficult to express the peak gain in explicit form. To simplify the analysis and design, the peak gains are obtained using simulation tools and depicted in Figure 14, which shows how the peak gain (attainable maximum gain) varies with Q for different m values. It appears that higher peak gain can be obtained by reducing m or Q values. With a given resonant frequency (fo) and Q value, decreasing m means reducing the magnetizing inductance, which results in increased circulating current. Accordingly, there is a tradeoff between the available gain range and conduction loss. © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 6 AN4151 APPLICATION NOTE 4. Features of FSFR-series FSFR-series is an integrated Pulse Frequency Modulation (PFM) controller and MOSFETs specifically designed for Zero Voltage Switching (ZVS) half-bridge converters with minimal external components. The internal controller includes an under-voltage lockout, optimized high-side / low-side gate driver, temperature-compensated precise current controlled oscillator, and self-protection circuitry. Compared with discrete MOSFET and PWM controller solution, FSFR-series can reduce total cost, component count, size and weight, while simultaneously increasing efficiency, productivity, and system reliability. Table 1. 1 VDL Pin Description 2 This pin is the drain of the high-side MOSFET, typically connected to the input DC link voltage. This pin is for enable/disable and protection. When the voltage of this pin is above 0.6V, the IC operation is enabled. Meanwhile, CON when the voltage of this pin drops below 0.4V, gate drive signals for both MOSFETs are disabled. When the voltage of this pin increases above 5V, protection is triggered. This pin is to program the switching frequency. Typically, opto-coupler and resistor are connected to this pin to regulate the output voltage. This pin is to sense the current flowing through the low-side MOSFET. Typically negative voltage is applied on this pin. This pin is the control ground. 3 RT 4 5 6 7 8 1 VDL 2 34 5 6 7 8 9 HVcc 10 VCTR CS SG PG This pin is the power ground. This pin is connected to the source of the low-side MOSFET. This pin is the supply voltage of the control LVcc IC. No connection. This pin is the supply voltage of the highHVcc side drive circuit. This pin is the drain of the low-side VCTR MOSFET. Typically transformer is connected to this pin. NC 9 10 RT SG LVcc CON CS PG Figure 15. Package Diagram 1.5μ s Figure 16. Functional Block Diagram of FSFR-series © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 7 AN4151 APPLICATION NOTE Cr Rdamp Dboot Llks Llk p D1 Np Ns Rbias Vcc C LVcc RT Rmax Rmin RSS CSS LVcc VDL HVcc Co Rd CF RF Vo Lm Ns Vin (From PFC output) CDL CB CHVcc CON Control IC VCTR Integrated Llks D2 transformer KA431 CS CLPF SG PG RLPF Rsense Figure 17. Reference Circuit for Design Example of LLC Resonant Half-bridge Converter 5. Design Procedure In this section, a design procedure is presented using the schematic in Figure 17 as a reference. An integrated transformer with center tap, secondary side is used and input is supplied from power factor correction (PFC) preregulator. A DC/DC converter with 192W/24V output has been selected as a design example. The design specifications are as follows: - Nominal input voltage: 400VDC (output of PFC stage) - Output: 24V/8A (192W) - Hold-up time requirement: 20ms (50Hz line freq.) - DC link capacitor of PFC output: 220µF Vin min = VO. PFC 2 − 2 PinTHU CDL (13) where VO.PFC is the nominal PFC output voltage, THU is a hold-up time, and CDL is the DC link bulk capacitor. (Design Example) Assuming the efficiency is 92%, P 192 Pin = o = = 209W 0.92 E ff Vin max = VO.PFC = 400V [STEP-1] Define the system specifications As a first step, define the following specification. Estimated efficiency (Eff): The power conversion efficiency must be estimated to calculate the maximum input power with a given maximum output power. If no reference data is available, use Eff = 0.88~0.92 for lowvoltage output applications and Eff = 0.92~0.96 for highvoltage output applications. With the estimated efficiency, the maximum input power is given as: Vin min = VO. PFC 2 − = 4002 − 2 PinTHU CDL 2 ⋅ 209 ⋅ 20 × 10−3 = 349V 220 × 10−6 [STEP-2] Determine the Maximum and Minimum Voltage Gains of the Resonant Network As discussed in the previous section, it is typical to operate the LLC resonant converter around the resonant frequency (fo) to minimize switching frequency variation. Since the input of the LLC resonant converter is supplied from PFC output voltage, the converter should be designed to operate at fo for the nominal PFC output voltage. As observed in Equation 10, the gain at fo is a function of m (m=Lp/Lr). The gain at fo is determined by choosing that value of m. While a higher peak gain can be obtained with a small m value, too small m value results in poor coupling of the transformer and deteriorates the efficiency. It is typical to set m to be 3~7, which results in a voltage gain of 1.1~1.2 at the resonant frequency (fo). www.fairchildsemi.com 8 Pin = Po E ff (11) Input voltage range (Vinmin and Vinmax): The maximum input voltage would be the nominal PFC output voltage as: Vin max = VO. PFC (12) Even though the input voltage is regulated as constant by PFC pre-regulator, it drops during the hold-up time. The minimum input voltage considering the hold-up time requirement is given as: © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 AN4151 APPLICATION NOTE With the chosen m value, the voltage gain for the nominal PFC output voltage is obtained as: [STEP-4] Calculate Equivalent Load Resistance With the transformer turns ratio obtained from Equation 16, the equivalent load resistance is obtained as: M min m @f=f = o m −1 (14) Rac = (Design Example) which would be the minimum gain because the nominal PFC output voltage is the maximum input voltage (Vinmax). The maximum voltage gain is given as: 8n 2 Vo 2 π 2 Po (17) Rac = (15) M max = Vin max min M Vin min 8n2 Vo 2 8 ⋅ 9.02 ⋅ 242 = = 197Ω π 2 Po π 2 ⋅ 192 [STEP-5] Design the Resonant Network With m value chosen in STEP-2, read proper Q value from the peak gain curves in Figure 14 that allows enough peak gain. Considering the load transient and stable zerovoltage-switching (ZVS) operation, 10~20% margin should be introduced on the maximum gain when determining the peak gain. Once the Q value is determined, the resonant parameters are obtained as: (Design Example) The ratio (m) between Lp and Lr is chosen as 5. The minimum and maximum gains are obtained as: VRO m 5 M min = max = = = 1.12 Vin 2 m −1 5 −1 M max = Vin max min 400 M= ⋅ 1.12 = 1.28 Vin min 349 Peak gain (available maximum gain) Cr = Gain (M) 1.28 for Vinmin 1 2π Q ⋅ f o ⋅ Rac 1 Lr = (2π f o ) 2 Cr (18) (19) (20) Mmax Lp = m ⋅ Lr (Design Example) Mmin 1.12 for ( VO.PFC ) Vinmax M= m = 1.12 m −1 fo Figure 18. Maximum Gain / Minimum Gain fs As calculated in STEP-2, the maximum voltage gain (M max) for the minimum input voltage (Vinmin) is 1.28. With 15% margin, a peak gain of 1.47 is required. m has been chosen as 5 in STEP-2 and Q is obtained as 0.4 from the peak gain curves in Figure 19. By selecting the resonant frequency as 100kHz, the resonant components are determined as: 1 1 Cr = = = 20.2nF 2π Q ⋅ f o ⋅ Rac 2π ⋅ 0.4 ⋅ 100 × 103 ⋅ 197 1 1 Lr = = = 126 μ H (2π f o ) 2 Cr (2π ⋅ 100 × 103 ) 2 ⋅ 20.2 × 10 −9 Lp = m ⋅ Lr = 630 μ H [STEP-3] Determine the Transformer Turns Ratio (n=Np/Ns) With the minimum gain (Mmin) obtained in STEP-2, the transformer turns ratio is given as: n= Np Ns = Vin max ⋅ M min 2(Vo + VF ) (16) where VF is the secondary-side rectifier diode voltage drop. (Design Example) assuming VF is 0.9V, n= Np Ns = 400 Vin max ⋅ M min = ⋅ 1.12 = 9.00 2(Vo + VF ) 2(24 + 0.9) Figure 19. Resonant Network Design Using the Peak Gain (Attainable Maximum Gain) Curve for m=5 © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 9 AN4151 APPLICATION NOTE [STEP-6] Design the Transformer The worst case for the transformer design is the minimum switching frequency condition, which occurs at the minimum input voltage and full-load condition. To obtain the minimum switching frequency, plot the gain curve using gain Equation 9 and read the minimum switching frequency. The minimum number of turns for the transformer primary-side is obtained as: 2.0 100% load 80% load 60% load 40% load 20% load 1.8 f min 1.6 f normal 1.4 Mmax 1.2 N p min = n(Vo + VF ) 2 f s ⋅ M V ⋅ ΔB ⋅ Ae min (21) 1.0 Mmin where Ae is the cross-sectional area of the transformer core in m2 and ΔB is the maximum flux density swing in Tesla, as shown in Figure 20. If there is no reference data, use ΔB =0.3~0.4 T. VRI 1/(2fs) n (Vo+VF)/MV 0.8 0.6 40 50 60 70 80 90 100 110 120 130 140 Frequency (kHz) Figure 21. Gain Curve [STEP-7] Transformer Construction -n (Vo+VF)/MV ΔB B Figure 20. Flux Density Swing Choose the proper number of turns for the secondary side that results in primary-side turns larger than Npmin as: N p = n ⋅ N s > N p min 2 (22) Parameters Lp and Lr of the transformer were determined in STEP-5. Lp and Lr can be measured in the primary side with the secondary-side winding open circuited and short circuited, respectively. Since LLC converter design requires a relatively large Lr, a sectional bobbin is typically used, as shown in Figure 22, to obtain the desired Lr value. For a sectional bobbin, the number of turns and winding configuration are the major factors determining the value of Lr, while the gap length of the core does not affect Lr much. Lp can be easily controlled by adjusting the gap length. Table 2 shows measured Lp and Lr values with different gap lengths. A gap length of 0.10mm obtains values for Lp and Lr closest to the designed parameters. Np N s2 N s1 (Design Example) EER3542 core (Ae=107mm ) is selected for the transformer. From the gain curve of Figure 21, the minimum switching frequency is obtained as 78kHz. The minimum primary-side turns of the transformer is given as: N p min = = n(Vo + VF ) 2 f s min ΔB ⋅ 1.11 ⋅ Ae 9.0 × 24.9 = 30.5 turns 2 ⋅ 77 × 103 ⋅ 0.4 ⋅ 1.11 ⋅ 107 × 10−6 Figure 22. Sectional Bobbin Choose Ns so that the resultant Np should be larger than Npmin: Table 2. Measured Lp and Lr with Different Gap Lengths Gap length Lp Lr N p = n ⋅ N s = 1 × 9.0 = 9 < N p min min N p = n ⋅ N s = 2 × 9.0 = 18 < N p N p = n ⋅ N s = 3 × 9.0 = 27 < N p min N p = n ⋅ N s = 4 × 9.0 = 36 > N p min 0.0mm 0.05mm 0.10mm 0.15mm 0.20mm 0.25mm 2,295μH 943μH 630μH 488μH 419μH 366μH 123μH 122μH 118μH 117μH 115μH 114μH © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 10 AN4151 APPLICATION NOTE (Design Example) Final Resonant Network Design VCr nom ≅ Vin max 2 ⋅ I Cr RMS + 2 2 ⋅ π ⋅ f o ⋅ Cr (24) Even though the integrated transformer approach in LLC resonant converter design can implement the magnetic components in a single core and save one magnetic component, the value of Lr is not easy to control in real transformer design. Resonant network design sometimes requires iteration with a resultant Lr value after the transformer is built. The resonant capacitor value is also changed since it should be selected among off-the-shelf capacitors. The final resonant network design is summarized in Table 3 and the new gain curves are shown in Figure 23. Table 3. Final Resonant Network Design Parameters Parameters Lp Lr Cr fo m Q M@fo Minimum freq Initial design 630µH 126H 20nF 100kHz 5 0.4 1.14 78kHz Final design 630µH 118µH 22nF 99kHz 5.34 0.36 1.11 72kHz However, the resonant capacitor voltage increases much higher than this at overload condition or load transient. Actual capacitor selection should be based on the OverCurrent Protection (OCP) trip point. With the OCP level, IOCP, the maximum resonant capacitor voltage is obtained as: VCr nom ≅ (Design Example) Vin max I OCP + 2 2 ⋅ π ⋅ f o ⋅ Cr (25) ICr RMS ≅ = 1 E ff [ π Io 2 n(Vo + VF ) ] +[ ]2 2 2n 4 2 fo M V ( L p − Lr ) 1 π ⋅8 2 9.0 ⋅ (24 + 0.9) [ ] +[ ]2 0.92 2 2 ⋅ 9.0 4 2 ⋅ 99 × 103 ⋅ 1.11 ⋅ 512 × 10−6 = 1.32 A The peak current in the primary side in normal operation is: I Cr peak = 2 ⋅ I Cr rms = 1.86 A OCP level is set to 3.0A with 50% margin on ICrpeak: VCr nom ≅ = VCr max Vin max 2 ⋅ I Cr RMS + 2 2 ⋅ π ⋅ f o ⋅ Cr 400 2 ⋅ 1.32 + = 336V 2 2 ⋅ π ⋅ 99 × 103 ⋅ 22 × 10−9 V max I OCP ≅ in + 2 2 ⋅ π ⋅ f o ⋅ Cr 400 3 + = 419V 2 2 ⋅ π ⋅ 99 ×103 ⋅ 22 ×10−9 = A 630V rated low-ESR film capacitor is selected for the resonant capacitor. Figure 23. Gain Curve of the Final Resonant Network Design [STEP-9] Rectifier Network Design [STEP-8] Select the Resonant Capacitor When choosing the resonant capacitor, the current rating should be considered because a considerable amount of current flows through the capacitor. The RMS current through the resonant capacitor is given as: When the center tap winding is used in the transformer secondary side, the diode voltage stress is twice of the output voltage expressed as: VD = 2(Vo + VF ) (26) I Cr RMS ≅ 1 E ff [ π Io 2 2n ]2 + [ n(Vo + VF ) ]2 (23) 4 2 fo M V ( L p − Lr ) The RMS value of the current flowing through each rectifier diode is given as: The nominal voltage of the resonant capacitor in normal operation is given as: © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 11 I D RMS = π 4 Io (27) www.fairchildsemi.com AN4151 APPLICATION NOTE Meanwhile, the ripple current flowing through output capacitor is given as: LVcc RT Rmax Rmin RSS CSS VDL ICo RMS = ( π Io 22 )2 − I o 2 = π2 −8 8 Io (28) The voltage ripple of the output capacitor is: ΔVo = π 2 Control IC I o ⋅ RC (29) External S/S SG PG Figure 24. Typical Circuit Configuration for RT Pin where RC is the effective series resistance (ESR) of the output capacitor and the power dissipation is the output capacitor is: PLoss.Co = ( I Co RMS ) 2 ⋅ RC (30) (Design Example) The voltage stress and current stress of the rectifier diode are: VD = 2(Vo + VF ) = 2(24 + 0.9) = 49.8 I D RMS = π 4 I o = 6.28 A The 100V/20A Schottky diode is selected for the rectifier considering the voltage overshoot caused by the stray inductance. The RMS current of the output capacitor is: I Co RMS = ( π Io 22 )2 − I o 2 = π2 −8 8 Soft-start: To prevent excessive inrush current and overshoot of output voltage during start-up, increase the voltage gain of the resonant converter progressively. Since the voltage gain of the resonant converter is reversely proportional to the switching frequency, the soft-start is implemented by sweeping down the switching frequency from an initial high frequency (f ISS) until the output voltage is established, as illustrated in Figure 25. The soft-start circuit is made by connecting RC series network on the RT pin as shown in Figure 24. FSFR-series also has an internal soft-start for 3ms to reduce the current overshoot during the initial cycles, which adds 40kHz to the initial frequency of the external soft-start circuit, as shown in Figure 25. The actual initial frequency of the soft-start is given as: I o = 3.857 A f ISS = ( When two electrolytic capacitors with ESR of 80mΩ are used in parallel, the output voltage ripple is given as: 5.2k Ω 5.2k Ω + ) × 100 + 40 (kHz ) (33) Rmin RSS ΔVo = π 2 I o ⋅ RC = π 2 ⋅8⋅( 0.08 ) = 0.50V 2 It is typical to set the initial frequency of soft-start (f ISS) as 2~3 times of the resonant frequency (fo). The soft-start time is determined by the RC time constant: The loss in electrolytic capacitors is: PLoss.Co = ( I Co RMS ) 2 ⋅ RC = 3.857 2 ⋅ 0.04 = 0.60W fs TSS = 3 ~ 4 times of RSS ⋅ CSS (34) f ISS [STEP-10] Control Circuit Configuration Figure 24 shows the typical circuit configuration for RT pin of FSFR-series, where the opto-coupler transistor is connected to the RT pin to control the switching frequency. The minimum switching frequency occurs when the optocoupler transistor is fully tuned off, which is given as: 40kHz Control loop take over 3ms 3~4 times of RC time constant time 5.2k Ω (31) f min = × 100( kHz ) Rmin Assuming the saturation voltage of opto-coupler transistor is 0.2V, the maximum switching frequency is determined as: f max = ( 5.2k Ω 4.68k Ω ) × 100(kHz ) + Rmin Rmax (32) Figure 25. Frequency Sweep of the Soft-start © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 12 AN4151 APPLICATION NOTE (Design Example) The minimum frequency is 72kHz in STEP-6. Rmin is determined as: I DS Rmin = 100 kHz × 5.2k Ω = 7.2k f min VCS Considering the output voltage overshoot during transient (10%) and the controllability of the feedback loop, the maximum frequency is set as 140kHz. Rmax is determined as: Cr VCS CS SG PG Control IC Np Ns Rmax 4.68k Ω = fo × 1.40 5.2k Ω ( − ) 100 kHz Rmin = 4.68k Ω = 7.1k Ω 99kHz × 1.4 5.2k Ω ( − ) 100 kHz 7.2k Ω Rsense Ns IDS Figure 27. Full-wave Sensing Setting the initial frequency of soft-start as 250kHz (2.5 times of the resonant frequency), the soft-start resistor RSS is given as: RSS = 5.2k Ω f ISS − 40kHz 5.2k Ω ( ) − 100kHz Rmin 5.2k Ω = 3.8k Ω 250kHz − 40kHz 5.2k Ω ( ) − 100kHz 7.2k Ω (Design Example) Since the OCP level is determined as 3A in STEP-8 and the OCP threshold voltage is 0.6V, a sensing resistor of 0.2Ω is used. The RC time constant is set to 100ns (1/100 of switching period) with 1kΩ resistor and 100pF capacitor. = [STEP-11] Current Sensing and Protection FSFR-series senses low-side MOSFET drain current as a negative voltage, as shown in Figure 26 and Figure 27. Half-wave sensing allows low-power dissipation in the sensing resistor, while full-wave sensing has less switching noise in the sensing signal. Typically, RC low-pass filter is used to filter out the switching noise in the sensing signal. The RC time constant of the low-pass filter should be 1/100~1/20 of the switching period. Cr Np Ns Ns Control IC VCS CS SG PG I DS Rsense IDS VCS Figure 26. Half-wave Sensing © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 13 AN4151 APPLICATION NOTE Design Summary Figure 28 shows the final schematic of the LLC resonant half-bridge converter design example. EER3542 core with sectional bobbin is used for the transformer. The efficiency at full load condition is around 94%. Figure 28. Final Schematic of Half-bridge LLC Resonant Converter - Core: EER3542 (Ae=107 mm2) - Bobbin: EER3542 (Horizontal/section type) EER3542 1 Np Ns1 1 3 1 2 Ns2 8 9 Np N s2 N s1 16 Figure 29. Transformer Structure Pin(S → F) Wire Turns Winding Method Np Ns1 Ns2 8→1 16 → 13 12 → 9 0.12φ×30 (Litz wire) 0.1φ×100 (Litz wire) 0.1φ×100 (Litz wire) 36 4 4 Section winding Section winding Section winding Pin Specification Remark Primary-side Inductance (Lp) Equivalent Leakage Inductance (Lr) 1－8 1－8 630μH ± 5% 118μH Max. Secondary windings open Short one of the secondary windings 100kHz, 1V 100kHz, 1V © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 14 AN4151 APPLICATION NOTE 6. Experimental Verification To show the validity of the design procedure presented in this application note, the converter of the design example has been built and tested. All the circuit components are used as designed in the design example. Figure 30 and Figure 31 show the operation waveforms at full-load and no-load conditions for nominal input voltage. As observed, the MOSFET drain-to-source voltage (VDS) drops to zero by resonance before the MOSFET is turned on and zero voltage switching is achieved. Figure 32 shows the waveforms of the resonant capacitor voltage and primary-side current at full-load condition. The peak values of the resonant capacitor voltage and primaryside current are 325V and 1.93A, respectively, which are well matched with the calculated values in STEP-8 of design procedure section. Figure 33 shows the waveforms of the resonant capacitor voltage and primary-side current at output-short condition. For output-short condition, over current protection (OCP) is triggered when the primaryside current exceeds 3A. The maximum voltage of the resonant capacitor is a little bit higher than the calculated value of 419V because the OCP trips at a level little bit higher than 3A, due to the shutdown delay time of 1.5µs (refer to the FSFR2100 datasheet). Figure 34 shows the rectifier diode voltage and current waveforms at full-load and no-load conditions. Due to the voltage overshoot caused by stray inductance, the voltage stress is a little bit higher than the value calculated in STEP-9. Figure 35 shows the output voltage ripple at fullload and no-load conditions. The output voltage ripple is well matched with the designed value in STEP-9. Figure 36 shows the measured efficiency for different load conditions. Efficiency at full-load condition is about 94%. Figure 31. Operation Waveforms at No-load Condition Figure 32. Resonant Capacitor Voltage and Primaryside Current Waveforms at Full-load Condition Figure 33. Resonant Capacitor Voltage and Primaryside Current Waveforms for Output Short Protection Figure 30. Operation Waveforms at Full-load Condition Figure 34. Rectifier Diode Voltage and Current Waveforms at Full-load Condition © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 15 AN4151 APPLICATION NOTE Figure 35. Output Voltage Ripple and Primary-side Current Waveforms at Full-load Condition Figure 37. Measured Efficiency Figure 36. Soft-start Waveforms © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 16 AN4151 APPLICATION NOTE 7. References [1] Robert L. Steigerwald, “A Comparison of Half-bridge resonant converter topologies,” IEEE Transactions on Power Electronics, Vol. 3, No. 2, April 1988. [2] A. F. Witulski and R. W. Erickson, “Design of the series resonant converter for minimum stress,” IEEE Transactions on Aerosp. Electron. Syst., Vol. AES-22, pp. 356-363, July 1986. [3] R. Oruganti, J. Yang, and F.C. Lee, “Implementation of Optimal Trajectory Control of Series Resonant Converters,” Proc. IEEE PESC ’87, 1987. [4] V. Vorperian and S. Cuk, “A Complete DC Analysis of the Series Resonant Converter,” Proc. IEEE PESC’82, 1982. [5] Y. G. Kang, A. K. Upadhyay, D. L. Stephens, “Analysis and design of a half-bridge parallel resonant converter operating above resonance,” IEEE Transactions on Industry Applications Vol. 27, March-April 1991, pp. 386 – 395. [6] R. Oruganti, J. Yang, and F.C. Lee, “State Plane Analysis of Parallel Resonant Converters,” Proc. IEEE PESC ’85, 1985. [7] M. Emsermann, “An Approximate Steady State and Small Signal Analysis of the Parallel Resonant Converter Running Above Resonance,” Proc. Power Electronics and Variable Speed Drives ’91, 1991, pp. 9-14. [8] Yan Liang, Wenduo Liu, Bing Lu, van Wyk, J.D, " Design of integrated passive component for a 1 MHz 1 kW halfbridge LLC resonant converter", IAS 2005, pp. 2223-2228. [9] B. Yang, F.C. Lee, M. Concannon, "Over current protection methods for LLC resonant converter" APEC 2003, pp. 605 - 609. [10] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhaoming Qian, Guisong Huang, "Three-level LLC series resonant DC/DC converter" IEEE Transactions on Power Electronics Vol.20, July 2005, pp.781 – 789. [11] Bo Yang, Lee, F.C, A.J Zhang, Guisong Huang, "LLC resonant converter for front end DC/DC conversion" APEC 2002. pp.1108 – 1112. [12] Bing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D. Van Wyk, “Optimal design methodology for LLC Resonant Converter,” APEC 2006. pp.533-538. Author Hang-Seok Choi / Ph. D FPS Application Group / Fairchild Semiconductor Phone: +82-32-680-1383 Fax: +82-32-680-1317 Email: hangseok.choi@fairchildsemi.com Related Datasheets FSFR2100 Important Notice DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 10/9/07 www.fairchildsemi.com 17