AN-6206

www.fairchildsemi.com AN-6206 Primary-Side Synchronous Rectifier (SR) Trigger Solution for Dual-Forward Converter Introduction In any switching converter, rectifier diodes are used to obtain DC output voltage. The conduction loss of diode rectifier contributes significantly to the overall power losses in a power supply; especially in low output voltage applications, such as personal computer (PC) power supplies. The conduction loss of a rectifier is proportional to the product of its forward-voltage drop and the forward conduction current. Using synchronous rectification (SR) where the rectifier diode is replaced by MOSFET with proper on resistance (RdsON), the forward-voltage drop of a synchronous rectifier can be lower than that of a diode rectifier and, consequently, the rectifier conduction loss can be reduced. The highly integrated FAN6210 is a primary-side SR controller for dual-forward converter that provides control signals for the secondary-side SR driver FAN6206. FAN6210 also provides drive signal for the primary-side power switches by using an output signal from the PWM controller. FAN6210 can be combined with any PWM controller that can drive a dual-forward converter. To obtain optimal timing for the SR drive signals, transformer winding voltage is also monitored. To improve light-load efficiency, green-mode operation is employed, which disables the SR turn-on trigger signal, minimizing gate drive power consumption at light-load condition. This application note describes the design procedure of SR circuit using FAN6210 and FAN6206. The guidelines for printed circuit board (PCB) layout and a design example with experiment results are also presented. Vin Vac PFC stage Cbulk Drv Lo n:1 R8 Q2 D1 Vo FAN6210 1 XP 2 XN PWM control signal (From PWM controller) 3 SIN GND 8 SOUT 7 VDD 6 Q1 R2 Drv R9 R6 R7 FAN6206 4 RDLY DET 5 R1 D5 D6 D3 D4 C1 D2 From power supply of PWM controller 1 LPC1GATE1 8 2 LPC2 GND 7 R3 R4 R5 PT 3 SN 4 SP GATE2 6 VDD 5 C2 Figure 1. Typical Application © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/27/10 www.fairchildsemi.com AN-6206 APPLICATION NOTE 1. FAN6210 External Component Setting Figure 2 and Figure 3 show the simplified schematic of two switch forward converters and their waveforms. The rectifying SR (SR1) should be turned on right after the primary-side MOSFETs are turned on. Then, SR1 should be turned off right before the primary-side MOSFETs are turned off. The freewheeling SR (SR2) should be turned on right after the primary-side MOSFETs are turned off. Then, SR2 should be turned off right before the primary-side MOSFETs are turned on. The primary-side SR trigger controller FAN6210 generates XN and XP signals, where XN rising edge triggers the turn-off of SR and XP rising edge triggers the turn-on of SR. FAN6210 generates XP and XN signals two times for each in one switching cycle and FAN6206 in the secondary side determines which SR MOSFET should be controlled for each XP and XN signals within one switching cycle. Figure 4 and Figure 5 show the detailed timing diagrams of XP and XN for the rising edge and falling edge of the SIN signal. The delay from the rising edge of SOUT to XP signal rising edge (tDLY_XP) is programmable using R1, as shown in Figure 1. The linear relationship between R1 and tDLY_XP is shown in Figure 6. The transformer winding voltage is much higher than the voltage rating of FAN6210 during PWM turn-on time. Therefore, R2 and D1 are used to block the high voltage, as shown in Figure 1. Since there is a 400ns DET falling-edge detection window after SOUT falls to prevent mistriggering of XP in DCM operation, too large value of R2 does not trigger XP properly due to too large RC time delay. It is typical to use 10kΩ~33kΩ for R2. The other requirement for triggering XP signal is that the HIGH level of the DET signal must be higher than 3V. To shorten the falling time from HIGH level to LOW level, the breakdown voltage of Zener diode D2 is recommended as 5~6V. Figure 2. Simplified Circuit Diagram of Dual-Forward Converter Figure 4. Timing Diagram During PWM Rising Edge Figure 3. Key Waveforms of Dual-Forward Converter Figure 5. Timing Diagram During PWM Falling Edge © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/27/10 www.fairchildsemi.com 2 AN-6206 APPLICATION NOTE To protect the XP and XN pins from transient voltage spikes; components R3, R4, D3, D4, D5, and D6 are necessary (shown in Figure 1). R3 and R4 are recommended as 10Ω. D3~D6 are chosen as Fairchild diode 1N4148. At the secondary side, R5 is connected between the SP and SN pins for reducing the overshoot caused by PT. The proper value of R5 is 1kΩ~10kΩ for most of applications. FAN6206 External Components Setting FAN6206 needs only four resistors to achieve winding detection and linear-predict control (LPC). Voltage divider with R6 and R7 detects the voltage across the drain-to-source terminal of Q1, while the other divider with R8 and R9 detects the voltage across the drain-to-source terminal of Q2. Figure 9 shows the typical waveform under CCM operation, which includes rectifying SR MOSFET drain voltage (Vds-R), freewheeling SR MOSFET drain voltage (Vds-F), inductor current (ILo), SR control signals (SP & SN), and SR gate signals. The detected signal on LPC1 and LPC2 pin determines the operation of synchronous rectification. The voltage divider scale-down factors are defined as: Figure 6. Programmable Delay with Resistor R1 2. Pulse Transformer (PT) The differential SR control XP-XN is delivered from FAN6210 to FAN6206 through a pulse transformer (PT), as shown in Figure 7. For the proper signal transfer, the core should have high initial permeability (μi). To separate primary-side and secondary-side windings, isolation is also necessary. It is typical to have the same number of turns for the primary and secondary to maximize the coupling. As the inductance of the winding decreases, the magnetizing increases, causing the voltage drop in the primary winding, as shown in Figure 8. The HIGH level of XP or XN signal should be higher than 4V to ensure proper SR gate driving. Meanwhile, too many turns may increase the inter-winding capacitance and, therefore, the inductance value should be determined properly. Typically, the inductance value is recommended as 100μH~300μH. RatioLPC1 = RatioLPC2 = R7 R6 + R7 R9 R8 + R9 (1) (2) 2.1 Rectifying SR Gate Drive Linear-predict control (LPC) is not essential for rectifying SR because rectifying SR is always turned off by the SN signal. Voltage divider with R6 and R7 is used to detect the HIGH/LOW status of Vds-R, as shown in Figure 9. The HIGH level threshold voltage for LPC1 is 2V, so the plateau voltage of LPC1 should be higher than 2V. To guarantee stable operation, the minimum plateau voltage of LPC1 is suggested to be 3V. However, LPC pin is a lowvoltage pin, so the proper operation range is from 3V to 5V. Therefore: Figure 7. Pulse Transformer Structure 3 < RatioLPC1 ⋅ Vin