AN-6300

www.fairchildsemi.com AN-6300 FAN6300 / FAN6300A / FAN6300H Highly Integrated Quasi-Resonant PWM Controller Abstract This application note describes a detailed design strategy for higher-power conversion efficiency and better EMI using a Quasi-Resonant PWM controller compared to the conventional, hard-switched converter with a fixed switching frequency. Based on the proposed design guideline, a design example with detailed parameters demonstrates the performance of the controller. range line voltage and reduces switching loss to minimize switching voltage on drain of the power MOSFET. To minimize standby power consumption and improve lightload efficiency, a proprietary green-mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. FAN6300/A/H controller provides many protection functions. Pulse-by-pulse current limiting ensures the fixed peak current limit level, even when short-circuit occurs. Once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. As long as VDD drops below the turn-off threshold voltage, the controller also disables the PWM output. The gate output is clamped at 18V to protect the power MOS from high gate-source voltage conditions. The minimum tOFF time limit prevents the system frequency from being too high. If the DET pin reaches OVP level, internal OTP is triggered, and the power system enters latch-mode until AC power is removed. Introduction The highly integrated FAN6300/A/H PWM controller provides several features to enhance the performance of flyback converters. FAN6300/A are applied on QuasiResonant flyback converter where maximum operating frequency is below 100kHz and FAN6300H is suitable for high frequency operation that is around 190kHz. A built-in High Voltage (HV) startup circuit can provide more startup current to reduce the startup time of the controller. Once the VDD voltage exceeds the turn-on threshold voltage, the HV startup function is disabled immediately to reduce power consumption. An internal valley voltage detector ensures power system operates in quasi-resonant operation in wide- © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 5/21/10 www.fairchildsemi.com AN-6300 APPLICATION NOTE Figure 1. Basic Quasi-Resonant Converter HV 8 4.2V IHV 27V Timer 55ms 2ms 30µs Starter FB OLP OVP VDD 6 Internal Bias Two Steps UVLO 16V/10V/8V FB 2 Soft-Start 5ms 2R Latched R CS 3 Blanking Circuit PWM Current Limit IDET Latched 0.3V VDET Valley Detector 1st Valley Latched DET OVP Internal OTP DRV S SET Q 18V 5 GATE Over-Power Compensation R CLR Q (3µs/13µs) for H version tOFF-MIN (8µs/38µs) tOFF-MIN +9µs tOFF-MIN +5µs for H version VDET tOFF S/H Blanking (4µs) 2.5V (1.5µs) for H version DET 1 5V IDET 0.3V Latched 4 GND 7 NC Figure 2. Functional Block Diagram © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 5/21/10 www.fairchildsemi.com 2 AN-6300 APPLICATION NOTE Design Procedure for the Primary-Side Inductance of Transformer In this section, a design procedure is described using the schematic of Figure 1 as a reference. designed to turn on the MOSFET when Vds reaches its minimum voltage Vin-n(Vo+Vd). [a] Define the System Specifications Line voltage range (Vin,min and Vin,max) Maximum output power (Po). Output voltage (Vo) and maximum output current (Io) Estimated efficiency (η) The power conversion efficiency must be estimated to calculate the maximum input power. In the case of NB adaptor applications, the typical efficiency is 85%~90%. With the estimated efficiency, the maximum input power is given by: n:1 + Vin n(Vo+Vd) + Coss + Vds + Vd + Vo - Pin = Po η (1) [b] Estimate Reflected Output Voltage Figure 3 shows the typical waveforms of the drain voltage of quasi-resonant flyback converter. When the MOSFET is turned off, the DC link voltage (Vo), together with the output voltage (Vo) and the forward voltage drop of the Schottky diode (Vd) reflected to the primary, are imposed on the MOSFET. The maximum nominal voltage across the MOSFET (Vds) is: Vds n(Vo+Vd) Vds n(Vo+Vd) n(Vo+Vd) Vin,max n(Vo+Vd) 0V Figure 3. Typical Waveform of MOSFET Drain Voltage for QR Operation Vds,max = Vin,max + n(Vo + Vd ) (2) Ids where the turns ratio of primary to secondary side of transformer is defined as n and Vds is as specified in Equation 2. By increasing n, the capacitive switching loss and conduction loss of the MOSFET is reduced. However, this increases the voltage stress on the MOSFET as shown in Figure 3. Therefore, determine n by a trade-off between the voltage margin of the MOSFET and the efficiency. Typically, a turn-off voltage spike of Vds is considered as 100V, thus Vds,max is designed around 490~550V (75~85% of MOSFET rated voltage). Iin Idspk Id DTs [c] Determine the Transformer Primary-side Inductance (LP) Figure 4 shows the typical waveforms of MOSFET drain current (Ids), secondary diode current (Id), and the MOSFET drain voltage (Vds) of a QR converter. During tOFF, the current flows through the secondary side rectifier diode. When Id reduces to zero, Vds begins to drop by the resonance between the effective output capacitor of the MOSFET and the primary-side inductance (LP). To minimize the switching loss, the FAN6300/A/H is © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 5/21/10 3 Vds n(Vo+Vd) Vin+n(Vo+Vd) Vin n(Vo+Vd) Vin-n(Vo+Vd) tOFF TS tF tON Figure 4. Typical Waveform of QR Operation www.fairchildsemi.com AN-6300 APPLICATION NOTE To determine the primary-side inductance (LP), the following variables should be determined beforehand: The minimum switching frequency (fs,min): The maximum average input current occurs at the minimum input voltage and full-load condition. Meanwhile, the switching frequency is at minimum value during QR operation. The falling time of the MOSFET drain voltage (tf): As shown in Figure 4, the falling time of MOSFET drain voltage is half of the resonant period of the MOSFET effective output capacitance and primaryside inductance. If a resonant capacitor is added to be paralleled with Coss, tf can be increased and EMI can be reduced. However, this forces a switching loss increase. The typical value of tf for NB adaptor application is about 0.5~1μs. After determining fs,min and tf, the maximum duty cycle is calculated as: [d] Determine the Proper Core and the Minimum Primary Turns When designing the transformer, consider the maximum flux density swing in normal operation (Bmax). The maximum flux density swing in normal operation is related to the hysteresis loss in the core, while the maximum flux density in transient is related to the core saturation. From Faraday’s law, the minimum number of turns for the transformer primary side is given by: NP,min = LP Ids,max pk Bmax Ae ×10 6 (9) where: LP is specified in Equation 7; Ids,maxpk is the peak drain current specified in Equation 6; Ae is the cross-sectional area of the core in mm2; and Bmax is the maximum flux density swing in tesla. Generally, it is possible to use Bmax =0.25~0.30 T. Dmax = n(Vo + Vd ) n(Vo + Vd ) + Vin × (1 - fs,min × tf ) (3) where Vin,min is specified at low-line and full-load. According to Equation 1, the maximum average input current Iin,max is determined as Determine the Number of Turns for Auxiliary Winding The number of turns for auxiliary winding (Na) can be obtained by: V + VD1 Na = DD (10) Vo + Vd where: VDD is the operating voltage for VDD pin; VD1 is the forward voltage drop of D1 in Figure 5; and Vo and Vd as determined in Equation 2. I in,max = Vo I o Vin,min η (4) According to Figure 3, Iin,max can be obtained as: I in,max = 1 2 Dmax Ids,max pk (5) Ids,maxpk can be determined as: I ds,max pk = Vin,min Dmax Lm fs,min (6) In Equation 5, replace Ids,maxpk by Equation 6, then combine Equations 4 and 5 to obtain LP: LP = (Vin,min Dmax ) 2Pin fs,min 2 (7) where Pin, and Dmax are specified in Equations 1 and 3, respectively, and fs,min is the minimum switching frequency. Once LP is determined, the RMS current of the MOSFET in normal operation are obtained as: I ds,max rms = Dmax 3 Ids,max peak (8) © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 5/21/10 www.fairchildsemi.com 4 AN-6300 APPLICATION NOTE Determine the Startup Circuitry When the power is turned on, the internal current (typically 1.2mA) charges the capacitor C1 through a forward diode D2 and a startup resistor RHV. During the startup sequence, the VAC from the AC terminal provides a startup current of about 1.2mA and charges the capacitor C1. RHV and D2 series connections can be directly connected by VAC to the HV pin. As the VDD pin reaches the turn-on threshold voltage VDD-ON, the FAN6300/A/H activates and signals the MOSFET. The HV startup circuit switches off and D1 is turned on when the energy of the main transformer is delivered to secondary and auxiliary winding. VDD-ON When the supply current is drawn from the transformer, it draws a leakage current of about 1μA for the HV pin. The maximum power dissipation of the RHV is: PR = IHV - LC(typ.) × RHV 2 HV (12) where IHV-LC is the supply current drawn from the HV pin. PR = 1μA2 x 100KΩ ≅ 0.1μW HV (13) The FAN6300/A/H has a voltage detector on the VDD pin to ensure that the chip has enough power to drive the MOSFET. Figure 7 shows a hysteresis of the turn-on and turn-off threshold levels. IDD 4.5mA VAC D2 R HV IHV 8 tD-ON D1 C1 80μA 10μA 8V 10V 16V VDD HV VDD 6 Figure 7. UVLO Specification FAN630 0/A/H GND 4 Figure 5. Startup Circuit for Power Transfer The maximum power-on delay time is determined as: The turn-on and turn-off threshold voltage are internally fixed at 16V and 10V. During startup, C1 must be charged to 16V to enable the IC. The capacitor continues to supply the VDD until the energy can be delivered from the auxiliary winding of the main transformer. The VDD must not drop below 10V during the startup sequence. If the secondary output short circuits or the feedback loop is open, the FB pin voltage rises rapidly toward the openloop voltage, VFB-OPEN. Once the FB voltage remains above VFB-OLP and lasts for tD-OLP, the FAN6300/A/H stops emitting output pulses. To further limit the input power under short-circuit or open-loop conditions, a special twostep UVLO mechanism has been built in to prolong this discharge time of the VDD capacitor. In Figure 8, the twostep UVLO mechanism decreases the operating current and pulls the VDD voltage toward the VDD-OFF. This sinking current is disabled after the VDD drops below VDD-OFF. The VDD voltage is again charged towards VDD-ON. With the addition of the two-step UVLO mechanism, the average input power during a short-circuit or open-loop condition is greatly reduced. When the gate pulses are emitted, the start-timer tSTARTER with 30μs per cycle is enabled. The 30μs start timer is enabled during startup until the output voltage is established, when the feedback voltage (VFB) is larger than 4.2V. t D −ON = C1 × VDD −ON (11) 1.2mA where VDD-ON is the FAN6300/A/H turn-on threshold voltage and tD-ON is the power-on delay time of the converter. If a shorter startup time is required, a two-step startup circuit, as shown in Figure 6, is recommended. In this circuit, a smaller C1 capacitor can be used to reduce the startup time. The energy supporting the FAN6300/A/H after startup is mainly from a larger capacitor C2. VDD-ON VAC D2 RHV IHV 8 tD-ON D1 C1 4 D2 C2 HV VDD 6 FAN6300/A/H GND Figure 6. Two-Step Circuit Providing Power © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 5/21/10 5 Figure 8. FAN6300/A/H UVLO Effect www.fairchildsemi.com AN-6300 APPLICATION NOTE Detection Pin Circuitry Figure 9 shows the DET pin circuitry. The DET pin is connected to an auxiliary winding by RDET and RA. The voltage divider is used for the following purposes: Detects the valley voltage of the switching waveform to achieve the valley voltage switching. This ensures QR operation, minimizes switching losses, and reduces EMI. Produces an offset to compensate the threshold voltage of the peak current limit to provide a constant power limit. The offset is generated in accordance with the input voltage with the PWM signal enabled. A voltage comparator and a 2.5V reference voltage provide an output OVP protection. The ratio of the divider determines what output voltage level to stop gate. RDET + VAUX RA 6 VDD DET 1 Figure 10. Voltage Sampled After 4µs(1.5µs for H version) Blanking Time After Switch-off Sequence DET 1 VDET tOFF S/H Blanking (4µs) 2.5V (1.5µs) for H version Latched DET OVP - 0.3V 5V To VDD + RDET Vo RA - Figure 9. Detection Pin Section First, determine the ratio of the voltage divider resisters. The ratio of the divider determines what output voltage level to stop gate. In Figure 10, the sampling voltage VS is: VS = NA NS ⋅VO ⋅ RA RDET + R A