AN-6961

www.fairchildsemi.com AN-6961 Critical Conduction Mode PFC Controller Description This application note describes a power factor correction (PFC) circuit using the FAN6961. Both the features of this controller, as well as the operation of the power factor correction circuit, are presented in detail. Based on the proposed design guideline, a design example with detailed parameters demonstrates the performance of the controller. Introduction The FAN6961 PFC controller is an 8-pin Boundary Current Mode (BCM) IC intended for controlling PFC pre-regulators. The FAN6961 provides a controlled on-time to regulate the output DC voltage and achieve natural power factor correction. The maximum on-time of the switch is programmable to ensure safe operation during AC brownouts. An innovative multi-vector error amplifier is built in to provide rapid transient response and precise output voltage clamping. Once the output feedback loop is opened, the output driver (GD) is disabled to provide protection of the system. The start-up current is lower than 20µA and the operating current has been reduced to 5mA. The supply voltage can be operated up to 25V, maximizing application flexibility. The FAN6961 also enables cycle-by-cycle current limiting protection for the external power MOSFET. Figure 1. Power Factor Correction Circuit © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 www.fairchildsemi.com AN-6961 APPLICATION NOTE Basic Operation of the Boost Converter The typical boost converter and its operational waveforms are shown in Figure 2, 3, and 4, respectively. Operation Principle Switch Q is ON: W hen Q turns on, the rectifier diode D is reverse-biased and output capacitor CO supplies load current. The rectified AC line input voltage Vg(t) is applied to the inductor Lb so that inductor current IL ramps up linearly and can be expressed as: Lb + v L (t ) − D + iL ( t ) vg (t ) − + Q Co Ro Vo − IL (ton ) = Vg (t) Lb (1) Figure 2. Boost Converter Lb + vL (t ) − Lb + vL (t ) − Switch Q is OFF: W hen Q turns off, the voltage VO-Vg(t) is applied to inductor Lb and the polarity on the inductor Lb is reversed. The diode D is forward-biased in this stage. The energy stored in the inductor Lb is delivered to supply load current and output capacitor CO. The inductor current iL can be expressed as: + vo − + iL ( t ) vg (t ) − Q + iL ( t ) vg (t ) − Co Ro IL (toff ) = Vo - Vg (t) Lb (2) (a) Switch Q is ON (b) Switch Q is OFF Figure 3. Switching Sequences of the Boost Converter vL (t ) vg (t ) v o − v g (t ) Controlled On-Time: The on-time of the power MOSFET Q is determined by the output of the error amplifier that monitors the preregulator output voltage. With a lowbandwidth error amplifier, the feedback signal is almost constant during a half AC cycle, resulting a fixed on-time of the power MOSFET at a specific AC voltage and some certain output power level. Therefore, the peak inductor current ILpk automatically follows the input voltage Vg(t), achieving a natural power factor correction mechanism. Figure 5 shows the typical inductor current waveform during a half AC cycle. iL (t ) vg (t ) Lb vo − vg (t ) Lb iL, pk iL , avg (t) v g (t ) iL,avg (t ) Q ton T toff Figure 4. One-cycle Waveform of the Boost Converter Gate on Off Tmin fixed On - Time Tmax Figure 5. Controlled On-Time Inductor Current Waveform Referring to Figure 4, considering one switching period the average inductor current IL,ave(t) can be calculated by the average area of triangle waveform of inductor current: ⎡ Vg (t)2 ⎤ ⎥• IL,avg (t ) = ⎢ Vg ( t ) + ⎢ Vo - Vg (t) ⎥ ⎣ ⎦ ⎡ ton ⎤ ⎢ ⎥ ⎣ Ts ⎦ • T s 2 • Lb 2 (3) © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 www.fairchildsemi.com 2 AN-6961 APPLICATION NOTE Block Operation Description Multi-Vector Error Amplifier The FAN6961 has a trans-conductance type amplifier that provides better dynamic performance. Referring to Figure 6, the error amplifier output VEA is compared with a sawtooth waveform to generate a fixed on-time. To achieve a low input current THD, the variation of the on-time within one input AC cycle should be very small. Therefore, the bandwidth of the feedback loop should be set below 20Hz to maintain a constant on-time for a line half-cycle. Connecting a capacitance CEA, such as 1µF, between COMP and GND is suggested. Total Harmonic Distortion (THD) Optimization As discusses previously, the FAN6961 uses the controlled on-time technique to achieve power factor correction mechanism. However, to get better THD at light load condition, especially at high input voltage, a THD optimization circuit is inserted into the FAN6961. With this internal THD optimization circuit, the on-time of the power MOSFET is modulated to further improve the THD performance. The calculated on-time variation within one line voltage period with the fixed on-time technique, and after the THD optimization is added, are shown in Figure 8. The calculated input current waveform is shown in Figure 9. THD Optimization(Vac=90V,Vo=250V) THD Optimization(Vac=264V,Vo=400V) Fixed On Time(Vac=90V,Vo=250V) Fixed On Time(Vac=264V,Vo=400V) PWM VEA _ out Sawtooth Generator Turn On Time(S) 1.85E-05 1.65E-05 1.45E-05 Gate t 1.25E-05 1.05E-05 8.50E-06 6.50E-06 ton Vds toff t 4.50E-06 2.50E-06 5.00E-07 0 20 40 60 80 Time(S/10000) 100 120 140 160 iL (t ) Vg (t ) Lb Vg ( t ) Vo - Vg (t ) Lb t Figure 8. MOS Turn-on Time Calculational Curve (Before and After THD Optimization Circuit Added) THD Optimization(Vac=90V,Vo=250V) THD Optimization(Vac=264V,Vo=400V) 2.0 Fixed On Time(Vac=90V,Vo=250V) Fixed On Time(Vac=264V,Vo=400V) t Figure 6. Operation Waveforms of Fixed On Time Technique Current(A) 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 20 40 60 80 Time(S/10000) For fast transient response and precise clamping of the output voltage overshoot and undershoot, the FAN6961 has a built-in multi-vector error amplifier. Figure 7 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds +6% and -8% of the reference voltage, the multi-vector error amplifier adjusts its output impedance to increase the loop response. 2.65V VO 2.3V Vref(2.5V) VEA_OUT CEA 2 COMP Error Amplifier FAN6961 INV 1 CO 100 120 140 160 Figure 9. Calculated Waveforms of the Input Current (Before and After THD Optimization Circuit Added) Figure 7. Block Diagram of the Multi-Vector Error Amplifier © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 www.fairchildsemi.com 3 AN-6961 APPLICATION NOTE Figure 10 shows the measured input current on the example circuit board. 1 2 Figure 12. Block Diagram of the Over / Under- Voltage Protection Zero-Current Detection Ch2: Before THD Optimization (1A/div); Ref1: After THD Optimization (1A/div) Figure 10. Calculated Waveforms of the Input Current (Before and After THD Optimization Circuit is Added) Figure 11 shows the measured THD performance on the example circuit board. THD Optimization 10 9 8 THD(%) 7 6 5 4 3 2 90 110 220 Vac(V) 240 264 Fixed On-Time Figure 13 shows the block diagram of the zero-current detection. The zero inductor current detection is performed by sensing the information on an auxiliary winding of the PFC inductor. As shown in Figure 14, when Q turns off, the stored energy of the inductor starts to release to the output. The voltage on the ZCD starts to decrease when the energy in the inductor dries out. Once the ZCD voltage is lower than the threshold voltage (1.75V typical), the PWM output is high again and initiates a new switching cycle. The output rectifier is always turned off with zero current, so the converter works in boundary mode conditions and the power MOSFET is switched on with low voltage to minimize the switching losses. Once the ZCD voltage is lower than the disable threshold voltage (around 0.25V) for a duration of about 800µs, the PWM output is disabled. To prevent high switching frequency during light load conditions, an inhibit timer function is built in to limit the maximum switching frequency. An RC filter (CZCD is around 0~22pF, RZCD is around 33K~68KΩ) connected from auxiliary winding to the ZCD pin is recommended to improve noise immunity on the ZCD pin. Figure 11. Measured THD Result at Full Load Condition (Fixed On-time Technique vs. THD Optimization) Over- / Under-Voltage Protection (OVP/UVP) Over / under-voltage protection is built-in to provide protection by detecting and examining the voltage on INV pin. When the voltage VINV exceeds 2.75V due to abnormal conditions, the internal OVP protection circuit is triggered to disable the PWM output. Over-voltage conditions are usually caused by an open-loop feedback. A debounce time around 35μs is added to prevent false triggering. If the voltage VINV is below 0.45V due to short-circuit conditions, PWM output is turned off. Figure 13. Block Diagram of the Zero-Current Detection © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 www.fairchildsemi.com 4 AN-6961 APPLICATION NOTE VZCD 10V Output Driver W ith a low on resistance and a high current driving capability, the output driver can drive an external capacitive load larger than 3000pF. Cross conduction currents are avoided to minimize heat dissipation, improving efficiency and reliability. This output driver is internally clamped by a 17V Zener diode. 2.1V 1.75V VDS VO t Lab Note Vg(t) 2Vg(t) - VO Before rework or solder/desolder on the power supply, discharge the primary capacitors by external bleeding resistor. Otherwise, the PWM IC may be destroyed by external high voltage during solder/desolder. Gate t Inhibit time Design Guideline PFC Inductor Design As shown in Figure 15, considering one AC line voltage cycle, the minimum switching frequency fs,min occurs at the peak of the AC line voltage. To avoid audible noise, the minimum switching frequency fs,min must be above audible frequency. The appropriate inductance can be calculated by Equation 5. The minimum switching frequency fs,min may happen in AC maximum or minimum input voltage, depending on the output voltage. Therefore, calculate both the maximum and the minimum input voltages, then choose the lower inductance value. Lb = t Figure 14. VDS & VZCD & Gate Waveform Maximum On-Time Operation The on-time of the power MOSFET is varied with the output power and the AC input voltage. While the AC input voltage decreases, the on-time increases accordingly. The maximum on-time limit ton,max can be programmed by the resistor connected between MOT and GND pin. ton,max = Rmot (kΩ ) • 25 (µs) 24 (4) η • Vpk 2 • Vo − Vpk 4 • Po • Vo • fs.min ( ) (5) The range of the maximum on-time is designed to be within 10~50μs; 25μs is recommended. VCC Over-Voltage Protection A VCC over-voltage protection avoids damage when the voltage VDD exceeds the internal threshold due to an openloop failure. Once the protection is triggered, the PWM output is turned off. where: Lb is the PFC inductor, η is conversion efficiency, Vpk is the peak of the AC line voltage, PO is rated output power, VO is PFC output voltage, fs,min is the minimum switching frequency. Switching Frequency Line input voltage[Vin(t)*200] Peak Current Limiting Switching Frequency(Hz) 7.00E+04 6.00E+04 5.00E+04 4.00E+04 3.00E+04 2.00E+04 1.00E+04 0.00E+00 0 10 20 30 40 Time(S/5000) 50 60 70 80 The switch current is sensed across a resistor and supplied to an input terminal of a comparator. A voltage higher than the 0.82V threshold voltage on the CS pin immediately terminates the current switching cycle, activating cycle-bycycle current limiting. Leading-Edge Blanking (LEB) A turn-on spike inevitably occurs at the CS pin when the power MOSFET is switched on. At the beginning of each switching pulse, the current-limit comparator is disabled for around 350ns to avoid premature termination. The gate drive output cannot be switched off during the blanking period. Figure 15. Frequency vs. Input Voltage The peak inductor current iLpk can be expressed as: i L,pk = 4 • Po 2 • Vrms. min • η Under-Voltage Lockout (UVLO) The turn-on and turn-off threshold voltages are fixed internally at 12V and 9.5V, respectively. This hysteresis behavior guarantees a one-shot start-up, as long as a proper start-up resistor and hold-up capacitor are used. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 (6) where Vrms.min is the minimum input line rms voltage. With the internal THD optimization circuit, the real peak inductor current is smaller than calculated. Usually, the real peak current is around 95% of calculated value. www.fairchildsemi.com 5 AN-6961 APPLICATION NOTE Determine Current-Sense Resistor The MOSFET on-time and the input current increase with the decreasing AC input voltage or increasing load. The FAN6961 can establish the maximum on-time limit (25µs is recommended) of power MOSFET. Once the voltage on current-sense pin reaches the internal limit VCS, 0.82V typically, the FAN6961 stops the PWM output immediately. Thus, the maximum output power can be designed by the current-sense resistor and maximum on-time limit. In general operation, the maximum on-time occurs at minimum AC input voltage and maximum loading conditions. When the output power increases from full load to maximum load, the on-time is restricted to the maximum ontime limit first, then the current limit. In the design example, the voltage on the current-sense pin is set to 0.57V at full load and minimum input voltage conditions. At this condition, the maximum power is about 156% of full load at minimum input voltage condition. The current-sense resistor can be calculated from Equation 7. The calculated curve of the MOSFET turn-on time at different loading conditions are shown in Figure 16. The calculated waveforms of the PFC inductor current at two kinds of current limit are shown in Figure 17. Full load Pin=105.9W 120% Full load Pin=127W Max. Pin=164.7W 2.60E-05 2.40E-05 2.20E-05 Turn On Time(uS) The FAN6961 current-sense limit, VCS, is 0.82V typically. From Faraday’s law, the number of turns for PFC inductor can be obtained by: Nb = Lb • IL,pk Bmax • A e • 106 (8) where: Ae is the effective area of the core-section, Bmax is saturation magnetic flux density. Determine the Auxiliary Winding The FAN6961 can perform zero-current detection by sensing the information on an auxiliary winding of the PFC inductor. As discussed previously, when the ZCD voltage is lower than the threshold voltage (1.75V typical), the PWM output is high again and initiates a new switching cycle. However, there is a prerequisite: the zero-current detector voltage must exceed the rising-edge threshold voltage (2.1V typical) before it falls below 1.75V. The minimum risingedge voltage of zero-current detector input occurs at the peak of the highest AC line voltage, which is equal to VO - 2 • Vrms,max / n and must be larger than the ZCD input rising-edge threshold voltage (2.1V typical). The ZCD voltage VZCD should be established as high as 120% of 2.3V to have a safe margin; therefore, the number of turns for auxiliary winding is obtained as: Naux = Vzcd • 1.2 Vo − 2 • Vrms. max • Nb 110% Full load Pin=116.46W 150% Full load Pin=158.8W (9) 2.00E-05 1.80E-05 1.60E-05 1.40E-05 1.20E-05 1 .00E-05 0 35 70 105 140 175 210 245 280 315 Current Sense Limit (0.82V/4.55A) where Vrms,max is the maximum input line rms voltage. VZCD is the rising-edge voltage of zero-current detector input. Max. On - Time Limit (25uS ) n :1 Time(S/20000) Figure 16. Calculated Curve of the MOSFET Turn-on Time at Different Loading Conditions Max. Pin=164.7W,Current Limit=4.55A Max. Pin=140.4W,Current Limit=3.727A 150% Full load Pin=158.8W, Current Limit=4.55A 5.00 4.50 4.00 PFC Inductor Current(A) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 35 70 105 140 175 210 245 280 315 Time(S/20000) Current Limit (4.55 A) Full load → Vcs = 0.57V Max. Load → 156% Full load Current Limit (3.727A) Full load → Vcs = 0.7V Max. Load → 133% Full Load Figure 18. Simplified Power Stage Calculate On-Time ton.fix The fixed on-time for the specific output power, inductor, and input voltage can be calculated by: ton.fix = 2 • Po • Lb Vrms 2 • η (10) Figure 17. Calculated Waveforms of the PFC Inductor Current at Two Current Limits where: Lb is the PFC inductor, η is conversion efficiency, PO is the maximum rated output power, Vrms is the input line rms voltage. www.fairchildsemi.com 6 0.57 RS = IL,PK • 95% © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 (7) AN-6961 APPLICATION NOTE Determine the Output Capacitor Co The output capacitor is determined by the requirement of sufficient hold-up time tHold: Co = 2 • Po • thold 2⎞ ⎛V 2 − V ⎜o o. min ⎟ • η ⎝ ⎠ (11) Reference Circuit The complete circuit diagram is shown in Figure 19 and the Bill of Materials for the PFC stage is shown in Table 2. Table 2. BOM List of PFC Stage Reference Components Reference Components where tHold is the output capacitor hold-up time, which is measured from the time the AC input turns off to before the output voltage falls below the minimum operating voltage of the following DC/DC stage. The output ripple voltage ΔVO is expressed as: ΔVo = Po ω • Co • Vo (12) F1 R1 R2 R3 R4 R5 R6 R7 R8 R13 R14 R15 4A/250V 510K 510K 10K 1M 18.7K 1M 430K 1M Open 24K 68K(47K) 10Ω 0Ω 0.18Ω/2W Open Open Open Open 0Ω 470V/7D 055 FAN6961 224pF C2 C3 C4 C5 C7 C8 C11 C12 C24 C25 C27 C28 C29 Q1 Q2 BD1 ZD1 D2 D3 L1 L2 L4 L5 0.33μ/275V Open Open Open 0.47μF/400V 0.47μF/400V 2.2μF/50V 68μF/450V 104pF Open Open Open(22p) 221pF 2N-7002 2SK-2482/ TO-220 KBP205G ZD24V R860/TO-220 1N4148 1mH 13mH RM-10/ 530µH 400μH where: ω = 2 π f, f is AC line frequency, IO is the output current. Determine the Compensation Capacitor CEA As discussed previously, to achieve a low input current THD, the variation of the on-time within one input AC cycle should be very small. To achieve this, the bandwidth should be lower than 20Hz. The capacitance CEA connected between COMP and GND can be obtained as: CEA = gm 2 • π • BW (13) R16 R17 R18 R55 R56 R57 R58 R59 MOV1 TR1 U1 C1 where BW is PFC control loop bandwidth and establishes it as 20Hz. The error amplifier is a trans-conductance amplifier that converts voltage to current with a 125µmho output conductance. Design Example This section shows a design example of a 90W (19V/4.74A) adaptor. From the specification, all critical components are treated and final measurement results are given. The basic design specification are shown as following: • • • • • AC Input Voltage Range Vrms: 90 ~ 264 VAC Rated Output Power PO: 90 W Minimum Switching Frequency fs,min: 35KHz High Regulated Output Voltage: 400V (at 180 ~ 264VAC) Low Regulated Output Voltage: 250V (at 90 ~ 132VAC) Based on the given design guideline, the critical parameters are calculated and summarized in Table 1: Table 1. Critical System Parameters Lb ipk Nb Naux CO CEA 530µH 3.327A 65T 7T 68µF/450V 1μF ton,fix(90Vrms) ton,fix(132Vrms) ton,fix(180Vrms) ton,fix(264Vrms) ΔVO(VO = 250V) ΔVO(VO = 400V) 13.86µs 6.44µs 3.46µs 1.61µs 14.043V 8.77V © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 www.fairchildsemi.com 7 AN-6961 APPLICATION NOTE Figure 19. Application Circuit Diagram (90W/19V) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/8/09 www.fairchildsemi.com 8