AN-8027

www.fairchildsemi.com AN-8027 FAN480X PFC+PWM Combination Controller Application FAN4800A / FAN4800C / FAN4801 / FAN4802 / FAN4802L Introduction This application note describes step-by-step design considerations for a power supply using the FAN480X controller. The FAN480X combines a PFC controller and a PWM controller. The PFC controller employs average current mode control for Continuous Conduction Mode (CCM) boost converter in the front end. The PWM controller can be used in either current mode or voltage mode for the downstream converter. In voltage mode, feed-forward from the PFC output bus can be used to improve the line transient response of PWM stage. In either mode, the PWM stage uses conventional trailingedge duty cycle modulation, while the PFC uses leadingedge modulation. This proprietary leading/trailing-edge modulation technique can significantly reduce the ripple current of the PFC output capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). In addition to power factor correction, a number of protection features have been built in to the FAN480X. These include programmable soft-start, PFC over-voltage protection, pulse-by-pulse current limiting, brownout protection, and under-voltage lockout. FAN4801/2/2L feature programmable two-level PFC output to improve efficiency at light-load and low-line conditions. FAN480X is pin-to-pin compatible with FAN4800 and ML4800, only requiring adjustment of some peripheral components. The FAN480X series comparison is summarized in the Appendix A. F1 AC Input L BOOST DBOOST CBOOST Q1 VBOUT R FB1 Drv L1 1 Q2 DR1 DR1 DF1 L1 2 CIF1 Vo1 Drv RCS1 R RAMP D1 D2 DR2 Drv CO11 CO12 L22 L DF2 2 1 Vo2 Q3 DR2 CO21 CO22 CIC2 RLF1 RT RRMS2 CLF1 CSS RB RLF2 RCS2 R IAC RIC IEA IAC ISENSE VRMS SS FBPWM RRMS1 CRMS1 CIC1 VEA FBPFC VREF VD D OPFC OPWM GND ILIMIT RD Vo 1 RBIAS VD D RVC CVC2 CVC1 CF RF ROS1 Vo2 CRMS2 R RMS3 CT RT/CT RAMP ROS2 ROS3 FAN480X CRAMP CB RFB2 CFB CLF2 CDD CREF Figure 1. Typical Application Circuit of FAN480X © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com AN-8027 Functional Description Gain Modulator The gain modulator is the key block for PFC stage because it provides the reference to the current control error amplifier for the input current shaping, as shown in Figure 2. The output current of gain modulator is a function of VEA, IAC , and VRMS. The gain of the gain modulator is given in the datasheet as a ratio between IMO and IAC with a given VRMS when VEA is saturated to HIGH. The gain is inversely proportional to VRMS2, as shown in Figure 3, to implement line feed-forward. This automatically adjusts the reference of current control error amplifier according to the line voltage such that the input power of PFC converter is not changed with line voltage. VIN IL However, once PFC stops switching operation, the junction capacitance of bridge diode is not discharged and VIN of Figure 2 is clamped at the peak of the line voltage. Then, the voltage of VRMS pin is given by: VRMS NS = VLINE 2 RRMS 3 RRMS 1 + RRMS 2 + RRMS 3 (2) Therefore, the voltage divider for VRMS should be designed considering the brownout protection trip point and minimum operation line voltage. PFC runs VIN PFC stops IEA R ISENS E RRMS1 RIAC CRMS1 CRMS2 IAC IA C VRMS VEA k x 2 M R M IMO = G ⋅ I AC = I AC ⋅ K ⋅ (VEA − 0.7) VRMS 2 (VEA MAX − 0.7) VRMS RRMS2 RRMS3 Gain Modulator Figure 4. VRMS According to the PFC Operation Figure 2. Gain Modulator Block The rectified sinusoidal signal is obtained by the current flowing into the IAC pin. The resistor RIAC should be large enough to prevent saturation of the gain modulator as: 2VLINE . BO ⋅ G MAX < 159μ A (3) RIAC where VLINE.BO is the line voltage that trips brownout protection, GMAX is the maximum modulator gain when VRMS is 1.08V (which can be found in the datasheet), and 159µA is the maximum output current of the gain modulator. G∝ 1 VRMS 2 Current and Voltage Control of Boost Stage As shown in Figure 5, the FAN480X employs two control loops for power factor correction: a current control loop and a voltage control loop. The current control loop shapes inductor current, as shown in Figure 6, based on the reference signal obtained at the IAC pin as: VRMS VRMS-UVP Figure 3. Modulation Gain Characteristics I L ⋅ RCS1 = I MO ⋅ RM = I AC ⋅ G ⋅ RM (4) To sense the RMS value of the line voltage, an averaging circuit with two poles is typically employed, as shown in Figure 2. The voltage of VRMS pin in normal PFC operation is given as: VRMS = VLINE 2 RRMS 3 2 ⋅ RRMS 1 + RRMS 2 + RRMS 3 π (1) where VLINE is RMS value of line voltage. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 2 AN-8027 V IN IL VO It is typical to set the second boost output voltage as 340V~300V. RCS1 RF1 ISENSE RRMS1 RIAC CRMS1 CRMS2 IAC CF1 IAC VRMS VEA RVC RVC2 FBPFC RVC1 2.5V RFB2 + RM RM IEA RIC IMO CIC2 Drive logic CIC1 RRMS2 VREF RRMS3 - OPFC RFB1 Figure 7. Block of Two-Level PFC Output Oscillator The internal oscillator frequency of FAN480X is determined by the timing resistor and capacitor on RT/CT pin. The frequency of the internal oscillator is given by: fOSC = 1 0.56 ⋅ RT ⋅ CT + 360CT (6) Figure 5. Gain Modulation Block IAC I MO RM RCS1 IL Figure 6. Inductor Current Shaping The voltage control loop regulates PFC output voltage using internal error amplifier such that the FBPFC voltage is same as internal reference of 2.5V. Because the PWM stage of FAN480X generally uses a forward converter, it is required to limit the maximum duty cycle at 50%. To have a small tolerance of the maximum duty cycle, a frequency divider with toggle flip-flops is used, as illustrated in Figure 8. The operation frequency of PFC and PWM stage is one quarter (1/4) of the oscillator frequency. (For FAN4800C and FAN4802/2L, the operation frequencies for PFC and PWM stages are one quarter (1/4) and one half (1/2) of the oscillator frequency, respectively). The dead time for the PFC gate drive signal is determined by the equation: tDEAD = 360CT (7) Brownout Protection FAN480X has a built-in internal brownout protection comparator monitoring the voltage of the VRMS pin. Once the VRMS pin voltage is lower than 1.05V (0.9V for FAN4802L), the PFC stage is shutdown to protect the system from over current. The FAN480X starts up the boost stage once the VRMS voltage increases above 1.9V (1.65V for FAN4802L). The dead time should be smaller than 2% of switching period to minimize line current distortion around line zero crossing. Two-Level PFC Output To improve system efficiency at low AC line voltage and light load condition, FAN480X provides two-level PFC output voltage. As shown in Figure 7, FAN480X monitors VEA and VRMS voltages to adjust the PFC output voltage. When VEA and VRMS are lower than the thresholds, an internal current source of 20µA is enabled that flows through RFB2, increasing the voltage of the FBPFC pin. This causes the PFC output voltage to reduce when 20µA is enabled, calculated as: VREF RT/ CT T-FF TQ T-FF T Q OPFC, OPWM OSC OPWM (FAN4800C, FAN4802/2L) Figure 8. Oscillator Configuration VOPFC 2 = RFB1 + RFB 2 × (2.5 - 20 μA × RFB 2 ) RFB 2 (5) www.fairchildsemi.com 3 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 AN-8027 RT/ CT VBOUT REF 1.5V RAMP PWM + PFC dead time RRAMP OPFC CRAMP OPWM FBPWM OPWM (FAN4800C, FAN4802/2L) Figure 9. FAN480X Timing Diagram Figure 10. PWM Ramp Generation Circuit PWM Stage The PWM stage is capable of current-mode or voltagemode operation. In current-mode applications, the PWM ramp (RAMP) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage and is thereby representative of the current flowing in the converter’s output stage. ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP in such applications. For voltage-mode operation, RAMP can be connected to a separate RC timing network to generate a voltage ramp against which FBPWM voltage is compared. Under these conditions, the use of voltage feed-forward from the PFC bus can be used for better line transient response. No voltage error amplifier is included in the PWM stage, as this function is generally performed by a programmable shunt regulator, such as KA431, in the secondary-side. To facilitate the design of opto-coupler feedback circuitry, an offset voltage is built into the inverting input of PWM comparator that allows FBPWM to command a zero percent duty cycle when its pin voltage is below 1.5V. PWM Current Limit The ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. If the input voltage at this pin exceeds 1V, the output of the PWM is disabled until the start of the next PWM clock cycle. VIN OK Comparator The VIN OK comparator monitors the output of the PFC stage and inhibits the PWM stage if this voltage is less than 2.4V (96% of its nominal value). Once this voltage goes above 2.4V, the PWM stage begins to soft-start. PWM Soft-Start (SS) PWM startup is controlled by the soft-start capacitor. A 10µA current source supplies the charging current for the soft-start capacitor. Startup of the PWM is prohibited until the soft-start capacitor voltage reaches 1.5V. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 4 AN-8027 Design Considerations In this section, a design procedure is presented using the schematic in Figure 11 as reference. A 300W PC power supply application with universal input range is selected as a design example. The design specifications are summarized in 0. The two-switch forward converter is used for DC/DC converter stage. Design Specifications Rated Voltage of Output 1 Rated Current of Output 1 Rated Voltage of Output 2 Rated Current of Output 2 Rated Voltage of Output 3 Rated Current of Output 3 Rated Voltage of Output 4 Rated Current of Output 4 Rated Output Power Line Voltage Range Line Frequency Brownout Protection Line Voltage Overall Stage Efficiency VOUT1 = 5V IOUT1 = 9A Vout2 = 12V IOUT2 = 16.5A VOUT3 = -12V IOUT3 = 0.8A VOUT4 = 3.3V IOUT4 = 13.5A PO = 300W 85~264VAC 50Hz 72VAC η = 0.82 PWM Stage Efficiency Hold-up Time Minimum PFC Output Voltage Nominal PFC output voltage PFC Output Voltage Ripple PFC Inductor Ripple Current AC Input Voltage Frequency Switching Frequency Total Harmonic Distortion Magnetic Flux Density Current Density PWM Maximum Duty Cycle 5V Output Current Ripple 12V Output Current Ripple F1 AC Input L BOOST DBOOST CBOOST Q1 VBOUT R FB1 Drv ηPWM = 0.86 tHLD = 20ms 310V VO_PFC = 387V 12VPP dI = 40% fline = 50 ~ 60Hz fS = 65KHz α = 4% ΔB = 0.27T Dcma = 400C-m/A Dmax = 0.35 ILo1 = 44% ILo2 = 10% L1 1 Q2 DR1 DR1 DF1 L1 2 CIF1 Vo1 Drv RCS1 R RAMP D1 D2 DR2 Drv CO11 CO12 L22 L DF2 2 1 Vo2 Q3 DR2 CO21 CO22 CIC2 RLF1 RT RRMS2 CLF1 CSS RB RLF2 RCS2 Vo3 Vo4 R IAC RIC IEA RRMS1 CRMS1 CIC1 VEA FBPFC VREF VD D OPFC OPWM GND ILIMIT RD Vo1 IAC ISENSE VRMS SS FBPWM RBIAS VD D RVC CVC2 CVC1 CF RF ROS1 Vo2 CRMS2 R RMS3 CT RT/CT RAMP ROS2 ROS3 FAN480X CRAMP CB RFB2 CFB CLF2 CDD CREF Figure 11. Reference Circuit for Design Example © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 5 AN-8027 [STEP-1] Define System Specifications Since the overall system is comprised of two stages (PFC and DC/DC), as shown in Figure 12, the input power and output power of the boost stage are given as: PIN = POUT (Design Example) Since the switching frequency is 65kHz, CT is selected as 1nF. Then the maximum duty cycle of PFC gate drive signal is obtained as: DMAX . PFC = 1 − 360 ⋅ CT ⋅ f SW = 0.98 The timing resistor is determined as: 1 1 RT = ⋅ = 6.9k Ω 4 0.56 f SW CT η POUT (8) (9) PBOUT = η PWM where η is the overall efficiency and ηPWM is the forward converter efficiency. The nominal output current of boost PFC stage is given as: I BOUT = PIN [STEP-3] Line Sensing Circuit Design FAN480X senses the RMS value and instantaneous value of line voltage using the VRMS and IAC pins, respectively, as shown in Figure 13. The RMS value of the line voltage is obtained by an averaging circuit using low pass filter with two poles. Meanwhile, the instantaneous line voltage information is obtained by sensing the current flowing into IAC pin through RIAC. VIN IL POUT η PWM VBOUT PBOUT IBOUT POUT (10) Boost PFC VBOUT Forward DC/DC VOUT Figure 12. Two Stage Configuration (Design Example) PIN = POUT η = 300 0.82 = = 366W RRMS1 RIAC IAC IA C VRMS VIN 120/100Hz PBOUT = POUT 300 0.86 η PWM = 349W 300 0.86 ⋅ 387 CRMS1 CRMS2 RRMS2 VRMS fp1 RRMS3 fp2 I BOUT = POUT η PWM VBOUT = = 0.9 A [STEP-2] Frequency Setting The switching frequency is determined by the timing resistor and capacitor (RT and CT) as: 1 1 f SW ≅ ⋅ (11) 4 0.56 ⋅ RT ⋅ CT It is typical to use a 470pF~1nF capacitor for 50~75kHz switching frequency operation since the timing capacitor value determines the maximum duty cycle of PFC gate drive signal as: DMAX .PFC = 1 − TOFF .MIN = 1 − 360 ⋅ CT ⋅ f SW TSW (12) Figure 13. Line Sensing Circuits RMS sensing circuit should be designed considering the nominal operation range of line voltage and brownout protection trip point as: VRMS −UVL = VLINE .BO 2 RRMS 3 2 ⋅ RRMS 1 + RRMS 2 + RRMS 3 π 2 RRMS 3 RRMS 1 + RRMS 2 + RRMS 3 (13) (14) VRMS −UVH < VLINE .MIN where VRMS-UVL and VRMS-UVH are the brown OUT/IN thresholds of VRMS. It is typical to set RRMS2 as 10% of RRMS1. The poles of the low pass filter are given as: f P1 ≅ fP2 ≅ 1 2π ⋅ CRMS 1 ⋅ RRMS 2 1 2π ⋅ CRMS 2 ⋅ RRMS 3 (15) (16) www.fairchildsemi.com 6 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 AN-8027 To properly attenuate the twice line frequency ripple in VRMS, it is typical to set the poles around 10~20Hz. The resistor RIAC should be large enough to prevent saturation of the gain modulator as: 2VLINE . BO ⋅ G MAX < 159μ A (17) RIAC where VLINE.BO is the brownout protection line voltage, GMAX is the maximum modulator gain when VRMS is 1.08V (which can be found in the datasheet), and 159µA is the maximum output current of the gain modulator. (Design Example) The brownout protection threshold is The average of boost inductor current over one switching cycle at the peak of the line voltage for low line is given as: I L. AVG = 2 POUT VLINE .MIN ⋅η (20) Therefore, with a given current ripple factor (KRB=ΔIL/ILAVG), the boost inductor value is obtained as: LBOOST = VLINE .MIN 2 ⋅η VBOUT − 2VLINE 1 ⋅ ⋅ K RB ⋅ POUT VBOUT f SW 2 POUT K RB K )= ⋅ (1 + RB ) 2 VLINE .MIN ⋅η 2 (21) The maximum current of boost inductor is given as: I L PK = I L. AVG ⋅ (1 + (22) 1.05V (VRMS-UVL) and 1.9V (VRMS-UVH), respectively. Then, the scaling down factor of the voltage divider is: RRMS 3 V π = RMS −UVL ⋅ RRMS 1 + RRMS 2 + RRMS 3 VLINE . BO 2 2 (Design Example) With the ripple current specification (40%), the boost inductor is obtained as: LBOOST = = VLINE .MIN 2 ⋅η VBOUT − 2VLINE 1 ⋅ ⋅ K RB ⋅ POUT VBOUT f SW 852 ⋅ 0.82 387 − 2 ⋅ 85 10−3 ⋅ ⋅ = 524 μ H 0.4 ⋅ 300 387 65 = 1.05 π ⋅ = 0.0162 72 2 2 Then the startup of the PFC stage at the minimum line voltage is checked as: VLINE .MIN ⋅ 2 RRMS 3 = 85 ⋅ 2 ⋅ 0.0162 = 1.95 > 1.9V RRMS 1 + RRMS 2 + RRMS 3 The resistors of the voltage divider network are selected as RRMS1=2MΩ, RRMS1=200kΩ, and RRMS1=36kΩ. To place the poles of the low pass filter at 15Hz and 22Hz, the capacitors are obtained as: 1 1 CRMS1 = = = 53nF 2π ⋅ f P1 ⋅ RRMS 2 2π ⋅15 ⋅ 200 × 103 CRMS 2 ≅ 1 1 = = 200nF 2π ⋅ f P 2 ⋅ RRMS 3 2π ⋅ 22 ⋅ 36 × 103 The average of boost inductor current over one switching cycle at the peak of the line voltage for low line is obtained as: I L. AVG = 2 POUT 2 ⋅ 300 = = 6.09 A VLINE .MIN ⋅η 85 ⋅ 0.82 The maximum current of the boost inductor is given as: I L PK = = 2 POUT K ⋅ (1 + RB ) VLINE .MIN ⋅η 2 2 ⋅ 300 0.4 ⋅ (1 + ) = 7.31A 85 ⋅ 0.82 2 The condition for Resistor RIAC is: 2VLINE .BO MAX 2 ⋅ 72 ⋅ 9 RIAC > ⋅G = = 5.8M Ω 159 × 10−6 159 × 10−6 Therefore, 6MΩ resistor is selected for RIAC. [STEP-5] PFC Output Capacitor Selection The output voltage ripple should be considered when selecting the PFC output capacitor. Figure 14 shows the twice line frequency ripple on the output voltage. With a given specification of output ripple, the condition for the output capacitor is obtained as: CBOUT > I BOUT 2π ⋅ f LINE ⋅ VBOUT , RIPPLE [STEP-4] PFC Inductor Design The duty cycle of boost switch at the peak of line voltage is given as: DLP = VBOUT − 2VLINE VBOUT (23) (18) where IBOUT is nominal output current of boost PFC stage and VBOUT,RIPPLE is the peak-to-peak output voltage ripple specification. The hold-up time also should be considered when determining the output capacitor as: CBOUT > PBOUT ⋅ tHOLD VBOUT 2 − VBOUT , MIN 2 Then, the maximum current ripple of the boost inductor at the peak of line voltage for low line is given as: ΔI L = 2VLINE .MIN VBOUT − 2VLINE 1 ⋅ ⋅ LBOOST VBOUT f SW (19) (24) where PBOUT is nominal output power of boost PFC stage, tHOLD is the required holdup time, and VBOUT,MIN is the allowable minimum PFC output voltage during hold-up time. www.fairchildsemi.com 7 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 AN-8027 ID I D , AVG I D , AVG = I BOUT (1 − cos(4π ⋅ f LINE ⋅ t )) I BOUT VBOUT , RIPPLE = I BOUT 2π f LINE CBOUT Figure 15. Two-Level PFC Output Block VBOUT Figure 14. PFC Output Voltage Ripple The voltage divider network for the PFC output voltage sensing should be designed such that FBPFC voltage is 2.5V at nominal PFC output voltage: VBOUT × RFB 2 = 2.5V RFB1 + RFB 2 (26) (Design Example) With the ripple specification of 12VPP, the capacitor should be: CBOUT I BOUT 0.9 > = = 239 μ F 2π ⋅ f LINE ⋅ VBOUT , RIPPLE 2π ⋅ 50 ⋅12 (Design Example) Assuming the second level of PFC output voltage is 347V: RFB 2 = (1 − = (1 − VBOUT 2 2.5 )⋅ VBOUT 20 × 10−6 Since minimum allowable output voltage during one cycle line (20ms) drop-outs is 310V, the capacitor should be: CBOUT > PBOUT ⋅ t HOLD VOUT − VOUT , MIN 2 2 347 2.5 = 12.9k Ω )⋅ 387 20 × 10−6 13kΩ is selected for RFB2. RFB1 = ( =( VBOUT − 1) ⋅ RFB 2 2.5 = 2 ⋅ 349 ⋅ 20 × 10−3 387 − 310 2 2 = 260 μ F Thus, 270μF capacitor is selected for the PFC output capacitor. 387 − 1) ⋅ 13 × 103 = 1999k Ω 2.5 2MΩ is selected for RFB1. [STEP-6] PFC Output Sensing Circuit To improve system efficiency at low line and light load condition, FAN480X provides two-level PFC output voltage. As shown in Figure 15, FAN480X monitors VEA and VRMS voltages to adjust the PFC output voltage. The PFC output voltage when 20µA is enabled is given as: VBOUT 2 = VBOUT × (1 20 μA × RFB 2 ) 2.5 (25) [STEP-7] PFC Current-Sensing Circuit Design Figure 16 shows the PFC compensation circuits. The first step in compensation network design is to select the currentsensing resistor of PFC converter considering the control window of voltage loop. Since line feed-forward is used in FAN480X, the output power is proportional to the voltage control error amplifier voltage as: PBOUT (VEA ) = PBOUT MAX ⋅ VEA − 0.6 VEA SAT − 0.6 (27) It is typical second boost output voltage as 340V~300V. where VEASAT is 5.6V and the maximum power limit of PFC is: PBOUT MAX = VLINE . BO 2 ⋅ G MAX ⋅ RM RIAC RCS 1 (28) © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 8 AN-8027 It is typical to set the maximum power limit of PFC stage around 1.2~1.5 of its nominal power such that the VEA is around 4~4.5V at nominal output power. By adjusting the current-sensing resistor for PFC stage, the maximum power limit of PFC stage can be programmed. To filter out the current ripple of switching frequency, an RC filter is typically used for ISENSE pin. RLF1 should not be larger than 100Ω and the cut-off frequency of filter should be 1/2~1/6 of the switching frequency. Diodes D1 and D2 are required to prevent over-voltage on ISENSE pin due to the inrush current that might damage the IC. A fast recovery diode or ultra fast recovery diode is recommended. where VRAMP is the peak to peak voltage of ramp signal for current control PWM comparator, which is 2.55V. The transfer function of the compensation circuit is given as: s 1+ ) 2π f IC vIEA 2π f II ⋅ )= s vCS 1 s 1+ 2π f IP where: f II = f IP = GMI 1 and , f IZ = 2π ⋅ CIC1 2π ⋅ RIC ⋅ CIC1 1 2π ⋅ RIC ⋅ CIC 2 (31) (32) The procedure to design the feedback loop is as follows: (a) Determine the crossover frequency (fIC) around 1/10~1/6 of the switching frequency. Then calculate the gain of the transfer function of Equation (30) at crossover frequency as: ) vCS1 ) vIEA = @ f = f IC RCS1 ⋅ VBOUT VRAMP ⋅ 2π f IC ⋅ LBOOST (33) (b) Calculate RIC that makes the closed loop gain unity at crossover frequency: RIC = 1 ) v GMI ⋅ )CS1 vIEA (34) @ f = f IC Figure 16. Gain Modulation Block (Design Example) Setting the maximum power limit of PFC stage as 450W, the current sensing resistor is obtained as: RCS 1 = VLINE .BO 2 ⋅ G MAX ⋅ RM 722 ⋅ 9 ⋅ 5.7 × 103 = = 0.098Ω 6 × 106 ⋅ 450 RIAC PBOUT MAX (c) Since the control-to-output transfer function of power stage has -20dB/dec slope and -90o phase at the crossover frequency is 0dB, as shown in Figure 17; it is necessary to place the zero of the compensation network (fIZ) around 1/3 of the crossover frequency so that more than 45° phase margin is obtained. Then the capacitor CIC1 is determined as: CIC1 = 1 RIC ⋅ 2π fC / 3 (35) Thus, 0.1Ω resistor is selected. [STEP-8] PFC Current Loop Design The transfer function from duty cycle to the inductor current of boost power stage is given as: ) iL V ) = BOUT (29) d sLBOOST The transfer function from the output of the current control error amplifier to the inductor current-sensing voltage is obtained as: ) vCS 1 RCS 1 ⋅ VBOUT (30) )= vIEA VRAMP ⋅ sLBOOST © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 (d) Place compensator high-frequency pole (fCP) at least a decade higher than fIC to ensure that it does not interfere with the phase margin of the current loop at its crossover frequency. CIC 2 = 1 2π ⋅ f IP ⋅ RIC (36) www.fairchildsemi.com 9 AN-8027 60dB Control-to-output 40dB 20dB 0dB -20dB -40dB 10Hz 100Hz Compensation Closed Loop Gain fIP fIZ fIC 1kHz 10kHz 100kHz 1MHz Figure 17. Current Loop Compensation Figure 18. Voltage Loop Compensation (Design Example) Setting the crossover frequency as 7kHz: ) vCS 1 RCS 1 ⋅ VBOUT = ) vIEA @ f = f VRAMP ⋅ 2π f IC ⋅ LBOOST IC The transfer function of the compensation network is obtained as: 0.1 ⋅ 387 = = 0.66 2.55 ⋅ 2π ⋅ 7 × 103 ⋅ 524 × 10 −6 RIC = ) v GMI ⋅ )CS 1 vIEA 1 = @ f = f IC s 1+ ˆ 2π fVZ vCOMP 2π fVI = ⋅ s ˆ vOUT s 1+ 2π fVP where: fVI = fVP = GMV 2.5 1 , fVZ = ⋅ 2π ⋅ RVC ⋅ CVC1 VBOUT 2π ⋅ CVC1 1 2π ⋅ RVC ⋅ CVC 2 and (39) 1 = 17 k Ω 88 × 10−6 ⋅ 0.66 (40) C IC1 = 1 1 = = 4nF RIC ⋅ 2π fC / 3 17 × 103 ⋅ 2π ⋅ 7 × 103 / 3 The procedure to design the feedback loop is as follows: (a) Determine the crossover frequency (fVC) around 1/10~1/5 of the line frequency. Since the control-tooutput transfer function of power stage has -20dB/dec slope and -90o phase at the crossover frequency, as shown in Figure 18 as 0dB; it is necessary to place the zero of the compensation network (fVZ) around the crossover frequency so that 45° phase margin is obtained. Then, the capacitor CVC1 is determined as: GMV ⋅ I BOUT ⋅ K MAX 2.5 ⋅ (41) 5 ⋅ C BOUT ⋅ (2π fVC ) 2 VBOUT To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: CVC1 = RVC = 1 2π ⋅ fVC ⋅ CVC1 (42) Setting the pole of the compensator at 70kHz, CIC 2 = 1 2π ⋅ f IP ⋅ RIC = 1 = 0.13nF 2π ⋅ 70 × 103 ⋅ 17 × 103 [STEP-9] PFC Voltage Loop Design Since FAN480X employs line feed-forward, the power stage transfer function becomes independent of the line voltage. Then, the low-frequency, small-signal, control-tooutput transfer function is obtained as: ˆ vBOUT I BOUT ⋅ K MAX ≅ ˆ 5 vEA where: ˆ vBOUT I BOUT ⋅ K MAX ≅ ˆ 5 vEA ⋅ 1 sCBOUT 1 sCBOUT (37) ⋅ (38) (b) Proportional and integration (PI) control with highfrequency pole is typically used for compensation. The compensation zero (fVZ) introduces phase boost, while the high-frequency compensation pole (fVP) attenuates the switching ripple, as shown in Figure 18. Place compensator high-frequency pole (fVP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter so noise can be effectively attenuated. Then, the capacitor CVC2 is determined as: 1 2π ⋅ fVP ⋅ RVC (43) CVC 2 = © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 10 AN-8027 (Design Example) Setting the crossover frequency as 22Hz: CVC1 = = RVC = GMV ⋅ I BOUT ⋅ K MAX 2.5 ⋅ 5 ⋅ C BOUT ⋅ (2π fVC ) 2 VBOUT 70 × 10 −6 ⋅ 0.9 ⋅1.27 2.5 ⋅ = 20nF −6 2 5 ⋅ 270 × 10 ⋅ (2π ⋅ 22) 387 1 1 = = 362k Ω 2π ⋅ fVC ⋅ CVC1 2π ⋅ 22 ⋅ 20 × 10−9 Once the core for the transformer is determined, the minimum number of turns for the transformer primary-side to avoid saturation is given by: MIN V DMAX N P MIN = BOUT (44) Ae f SW ΔB where Ae is the cross sectional area of the core in m2, fSW is the switching frequency, and ΔB is the maximum flux density swing in Tesla for normal operation. ΔB is typically 0.2-0.3 T for most power ferrite cores in the case of a forward converter. The turn ratio between the primary-side and secondary-side winding for the first output is determined by: MIN N V DMAX n = P = BOUT (45) (VO1 + VF 1 ) N S1 where VF is the diode forward-voltage drop. Next, determine the proper integer for NS1 resulting in Np larger than Npmin. Once the number of turns of the first output is determined, the number of turns of other output (n-th output) can be determined by: VO ( n ) + VF ( n ) N S (n) = ⋅ N S1 (46) VO1 + VF 1 The golden ratio between the secondary-side windings for the best regulation of 3.3V, 5V, and 12V is known as 2:3:7. (Design Example) The minimum PFC output voltage is 310V and the maximum duty cycle of PWM controller is 50%. By adding 5% margin to the maximum duty cycle, DMAX=0.45 is used for transformer design. Assuming ERL35 (Ae=107mm2) core is used and ΔB=0.28, the minimum turns for the transformer primary side is obtained as: N P MIN = VBOUT MIN DMAX 310 ⋅ 0.45 = = 72 Ae f SW ΔB 107 × 10 −6 ⋅ 65 × 103 ⋅ 0.28 Setting the pole of the compensator at 120Hz: CVC 2 = 1 2π ⋅ fVP ⋅ RVC = 1 = 3.7 nF 2π ⋅ 120 ⋅ 362 × 103 [STEP-10] Transformer Design for PWM Stage Figure 19 shows the typical secondary-side circuit of forward converter for multi-output of PC power application. A common technique for winding multiple outputs with the same polarity sharing a common ground is to stack the secondary windings instead of winding each output winding separately. This approach improves the load regulation of the stacked outputs. The winding NS1 in Figure 19 must be sized to accommodate its output current, plus the current of the output (+12V) stacked on top of it. To get tight regulation of 3.3V output, magnetic amplifier (MAG-AMP) is used. The saturable core of MAG-AMP prevents the diode DREC from fully conducting by introducing high impedance until it is saturated. This allows the effective duty cycle of VREC to be controlled to be regulated the output voltage. Additiona l LC filter +12V NS 2 The turns ratio for 5V output is obtained as: Additiona l LC filter n= +5V Np NS 1 N P VBOUT MIN DMAX 310 ⋅ 0.45 = = = 25.6 (VO + VF ) (5 + 0.45) NS The number of turns for the primary-side winding is determined as: MAG AMP Control +3.3 V MAG AMP N p = n ⋅ N S 1 = 2 × 25.6 = 51.2 < N P MIN N p = n ⋅ N S 1 = 3 × 25.6 = 76.8 > N P MIN ∴ N S 1 = 3 DREC + VREC - Additiona l LC filter Then, the turns ratio for 12V output is obtained as: NS 2 = VO 2 + VF 2 12 + 0.7 ⋅ N S1 = ⋅ 3 = 6.99 ≅ 7 5 + 0.45 VO1 + VF 1 NS 3 Additiona l LC filter -12V Therefore, the number of turns for each winding is obtained as: Np=78, NS1=3, NS2=7 (3+4 stack) and NS3=7. Figure 19. Typical Secondary-Side Circuit © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 11 AN-8027 [STEP-11] Coupled Inductor Design for the PWM Stage When the forward converter has more than one output, as shown in Figure 20, coupled inductors are usually employed to improve the cross regulation and to reduce the ripple. They are implemented by winding their separate coils on a single, common core. The turns ratio should be the same as the transformer turns ratio of the two outputs as: NS 2 NL2 = (47) N S 1 N L1 L2 N p NL2 VO2 One way to understand the operation of coupled inductor is to normalize the outputs to one output. Figure 21 shows how to normalize the second output (VO2) to the first output (VO1). The transformer and inductor turns are divided by NS2/NS1, the voltage and current are adjusted by NS2/NS1. It is assumed that the leakage inductances of the coupled inductor are much smaller than the magnetizing inductance and evenly distributed for each winding. The inductor value of the first output can be obtained by: VO1 (VO1 + VF 1 ) L1 = ⋅ (1 − DMIN ) ΔI (48) f SW ( PO1 + PO 2 ) SUM I SUM where: MIN V DMIN = DMAX BOUT VBOUT (49) PO1 + PO 2 I SUM = VO1 Then, the ripple current for each output is given as: ΔI O1 ΔI SUM 1 = ⋅ 2 I O1 I O1 N S2 NL1 L1 N S1 VO1 (50) (51) ΔI O 2 ΔI SUM N S 1 1 = ⋅ ⋅ 2 IO 2 N S 2 IO 2 Figure 20. Coupled Inductor D1 L1 VO1 IO1 (Design Example) The minimum duty cycle of PWM stage at nominal input (PFC output) voltage is: DMIN = DMAX VBOUT MIN 310 = 0.45 = 0.36 389 VBOUT VPOUT ⋅ N S1 NP 0 D2 The sum of two normalize output current is: VO2 L2 IO2 I SUM = VPOUT ⋅ N S 2 NP 0 PO1 + PO 2 243 = = 48.6 A VO1 5 Assuming 16% p-p ripple current in LSUM, the inductor for the first output is obtained as: L1 = Normalized VO 2 N = IO 2 N = ISUM N S1 VO 2 = VO1 NS 2 NS 2 IO 2 N S1 LM LLK D1 VO1 (VO1 + VF 1 ) ⋅ (1 − DMIN ) ΔI f SW ( PO1 + PO 2 ) SUM I SUM = VO1 IO2 5(5 + 0.45) ⋅ (1 − 0.36) = 6.9uH 65 × 103 (5 × 9 + 12 × 16.5) ⋅ 0.16 VPOUT ⋅ N S1 NP 0 D2N LLK Then, the ripple current for each output is given as: ΔI O1 ΔI SUM 1 48.6 × 0.16 1 = ⋅ = ⋅ = 43% 2 2 9 I O1 I O1 ΔI O 2 ΔI SUM N S 1 1 48.6 × 0.16 3 1 = ⋅ ⋅ = ⋅⋅ = 10% IO 2 N S 2 IO 2 2 2 7 16.5 VO2N IO2N Figure 21. Normalized Coupled Inductor Circuit © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 12 AN-8027 [STEP-12] PWM Ramp Circuit Design For voltage-mode operation, the RAMP pin can be connected to a DC voltage through a resistor. When it is connected to the input of forward converter, ramp signal slope is automatically adjusted according to the input voltage providing line feed-forward operation. However, it can cause more power dissipation in the resistor. For better efficiency and lower standby power consumption, it is recommended to connect the RAMP pin to the VREF pin. [STEP-13] Feedback Compensation Design for PWM Stage Figure 21 shows the typical cross regulation compensation circuit configuration for multi-output converters. The small signal characteristics of the compensation network is given as: ) vFBPWM =− 1 + s / ωCZ 1 ) 1 + s / ωCZ 2 ) RB ⋅( vO1 + vO 2 ) 1 + s / ωCP ROS 1 RD CF s ROS 2 RD CF s (53) where: ωCP = ωCZ 1 = ωCZ 2 = 1 ( RB1 // RB 2 )CB 1 RF C F 1 ( RF + ROS 2 )CF (54) VO2 VREF RB1 Figure 22. Ramp Generation Circuit for PWM VO1 ROS1 RD ROS2 FBPWM It is typical to use 470pF~1nF capacitor on the RAMP pin and to have the peak of the ramp signal around 2~3V. The peak of the ram voltage is given as: VRAMP PK = 1 CRAMP ⋅ VREF 1 ⋅ RRAMP 2 f SW RB RF CF (52) CB KA431 ROS3 (Design Example) Selecting CRAMP and RRAMP as 1nF and 22k, the PWM ramp voltage is obtained as: VRAMP PK = = 1 CRAMP ⋅ VREF 1 ⋅ RRAMP 2 f SW Figure 23. Feedback Compensation Circuit for PWM Stage 1 7.5 1 ⋅ ⋅ = 2.6V −9 3 1× 10 22 × 10 2 ⋅ 65 × 103 The small signal equivalent circuit for control-to-output transfer function of the PWM power stage can be simplified as shown in Figure 24. The transfer function is fourth-order system because additional LC filters are used to meet the output voltage ripple specification. Therefore, it is recommended to use engineering software, such as PSPICE or Mathlab, to design the feedback loop. VBOUT ⋅ N S1 NS 2 LM LLK LL12 VO1 CO11 1 VRAMP LLK CO21N L22N CO22N CO12 RL1 VO2N VO2 VFBPWM RL2N NS1:NS2 Figure 24. Simplified Small Signal Equivalent Circuit for Control-to-Output Transfer Function © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 13 AN-8027 Design Summary Application ATX Power Output Power 300W Input Voltage 85~264VAC Output Voltage / Output Current 12V/16.5A；5V/9A；-12V/0.8A ；3.3V/13.5A Features Meets 80+ specification FAN4800A fully pin-to-pin compatible with ML4800 and FAN4800 (needs few parts modify) Switch-charge technique of gain modulator can provide better PF and lower THD Leading and trailing modulation technique for reduce output ripple Protections: OVP (Over-Voltage Protection), UVP (Under-Voltage Protection), OLP (Open-Loop Protection), and maximum current limit 1.8uH L1 2 F1 AC Input L BOOST FDA18N50 DBOOST BYC10600 CBOOST VBOUT R FB1 2M 10 k 100 nF FCP11N60 FR157 FCP11N60 FYPF2006DN L1 1 DR1 Q2 DR1 FR157 Vo1 12V CO11 DF1 2200uF CO12 1000uF CIF1 5 Q1 270uF RCS1 0.1 DR2 L2 DF2 1 L22 2uH CO21 2200uF Vo2 5V CO22 1000uF D1 D2 STPS60L45CW SF34DG Vo3 -12V R RAMP 22k 10 k Q3 DR2 L3 1 0.13nF CIC2 2M RRMS1 53nF CRMS1 200 K RLF1 RT 6.9 k RRMS2 CLF1 CSS RB 7.5k RLF2 4nF CIC1 VEA CO31 RCS2 L4 1 220uF L43 L DF2 FR157 4 2 R IAC 6M 17k RIC IEA IAC ISENSE VRMS SS FBPWM CO21 CO22 10 1k 3.3V Vo4 FBPFC VREF VD D OPFC OPWM GND ILIMIT VD D 362k RVC 20nF CVC1 12.9k RFB2 3.7nF CVC2 1.2 k RD CF 100 nF 4.64 k RF 32.4 k ROS1 11 k ROS2 ROS3 5V Vo2 FR157 300 Vo1 12V 200n 36 k F CRMS2 R RMS3 3.4 k 1uF 10 k 5.45 k CT 1nF 0.47nF CB RT/CT RAMP 10 1nF CRAMP FAN480X CFB CLF2 CDD CREF Figure 25. Final Schematic of Design Example © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 14 AN-8027 Margin Tape 3mm Margin Tape 3mm Mylar Tape 3T N5 N4 N3 N2 Mylar Tape 1T Mylar Tape 1T Mylar Tape 1T Mylar Tape 3T N1 BOBBIN-ERL35 Figure 26. Forward Converter Transformer Structure Winding Specification No Pin(s-f) Wire N1 3-2 0.6Ф Insulation: Mylar Tape t = 0.03mm, 3 Layers N2 8,9-10,11,12 Copper-Foil 10mil Insulation: Mylar Tape t = 0.03mm, 1 Layers N3 13-8,9 1.0Ф*4 Insulation: Mylar Tape t = 0.03mm, 1 Layers N4 10,11,12-14 0.4Ф Insulation: Mylar Tape t = 0.03mm, 1 Layers N5 2-6,7 0.6Ф Insulation: Mylar Tape t = 0.03mm, 3 Layers Core-ERL35 Insulation: Mylar Tape t = 0.03mm, 3 Layers Insulation: Copper-Foil Tape t = 0.05mm-pin1 Open Loop Insulation: Mylar Tape t = 0.03mm, 3 Layers Turns 37Ts 3Ts 4Ts 6Ts 37Ts Winding Method Solenoid Winding Copper-Foil Width 18mm Solenoid Winding Solenoid Winding Solenoid Winding Core: ERL35 (Ae=107 mm2) Bobbin: ERL35 Inductance: 13mH © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 15 AN-8027 Appendix A FAN480X Series Comparison Table of Relevant Parameters FAN4800 New Generation FAN4800A New Generation FAN4800C New Generation FAN4801 New Generation FAN4802/2L VDD Maximum Rating VDD OVP VCC UVLO Two-Level PFC Output PFC Soft-Start Brownout PFC：PWM Frequency Frequency Range Gate Clamp PFC Multiplier VINOK PWM Maximum Duty Startup Current Soft-Start Current PWM Comparator Level Shift RAC 20V 17.9V/Clamp 10V/13V NO NO NO 1：1 68kHz~81kHz NO Traditional 2.25V/1.1V 42%~49% 100μA 20μA 1.0V 1~2MΩ 1：1 NO 30V 28/Auto-Recover 9.3/11V YES YES YES 1：2 1：1 1：2 50kHz~75kHz 16V Switching Charge 2.40V/1.15V 49.5%~50% 30μA 10μA 1.5V 5~8 MΩ MOSFET and Diode Reference Specification PFC MOSFETs Voltage Rating 500V 600V Part Number FQP13N50C, FQPF13N50C, FDP18N50, FDPF18N50, FDA18N50, FDP20N50(T), FDPF20N50(T) FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCP20N60S, FCPF20N60S, FCA20N60S, FCP20N60, FCPF20N60 Boost Diodes 600V FFP08H60S, FFPF10H60S, FFP08S60S, FPF08S60SN, BYC10600 PWM MOSFETs 500V 600V FQP/PF9N50C, FQPF9N50C, FQP13N50C, FQPF13N50C, FQA13N50C, FDP18N50, FDPF18N50, FDP20N50(T), FDPF20N50(T) FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCA16N60, FCP20N60S, FCPF20N60S, FCA20N60S, FCP20N60, FCPF20N60, FCA20N60 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 16 AN-8027 References FAN480X — PFC/Forward PWM Controller Combo (FAN4800, FAN4801, FAN4802) AN-6078SC — FAN480X PFC+PWM Combo Controller Application AN-6004 — 500W Power Factor Corrected (PFC) Design with FAN4810 AN-6032 — FAN4800 Combo Controller Applications AN-42030 — Theory and Application of the ML4821 Average Current Mode PFC Controller AN-42009 — ML4824 Combo Controller Applications ATX 300W 80+ Evaluation Board of FAN4800A+SG6520+FSQ0170 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.0 • 8/26/09 www.fairchildsemi.com 17