BYC10600

www.fairchildsemi.com AN-6982 Power Factor Correction Converter Design with FAN6982 Introduction The FAN6982 is a 14-pin, Continuous Conduction Mode (CCM) Power Factor Correction (PFC) controller IC, that employs leading-edge modulation for average current control and has a number of advanced features for better performance and reliability. The variable output voltage function (range function) reduces PFC output voltage at light-load and low-line conditions to improve light-load efficiency, but can be also easily disabled using EN pin. The RDY signal can be used for power-on sequence control of the downstream DC/DC converter. A TriFault Detect™ function helps reduce external components and provides full protection for feedback loops such as open, short, and over voltage. FAN6982 also includes PFC softstart, peak current limiting, line feed-forward, and input voltage brownout protection. This application note describes the theory of operation and step-by-step design considerations for a power factor correction power supply using the FAN6982 controller. A typical application circuit is shown in Figure 1, where the supply voltage, VDD, is supplied from a standby auxiliary power supply and the supply voltage for the downstream converter is controlled by the RDY pin. F1 AC Input CIF2 CIF1 LBOOST DBOOST VBOUT VOUT RDRV Q1 RCS D1 RLF RRMS1 CRMS1 RIAC RIC IEA IAC ISENSE VRMS CBOOST Downstream DC/DC Converter RPL D2 CIC2 CIC1 VEA FBPFC VREF VDD OPFC PGND SGND PWM Controller RFB1 vCC RRMS2 RRMS3 CLF RVC CVC2 CDD RFB2 CFB CVC1 Rreg1 CREF Rreg2 Rreg3 CRDY Q2 CRMS2 RDY EN RT/CT FAN6982 REN Range Enabled/Disabled VEN = VVREF : Enabled VEN = GND : Disabled CT RT From Standby Auxiliary Power Supply Figure 1. Typical FAN6982 Application Circuit © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com AN-6982 APPLICATION NOTE Functional Description Widely used operation modes for the boost converter are continuous conduction mode (CCM) and boundary conduction mode (BCM). These two descriptive names refer to the current flowing through the energy storage inductor of the boost converter, as depicted in Figure 2. The inductor current in CCM is continuous; while in BCM, the new switching period is initiated when the inductor current returns to zero, which is at the boundary of continuous conduction and discontinuous conduction operations. CCM PFC is commonly used for high-power applications above 300W since the inductor current has a small ripple and higher power factor can be obtained than BCM operation. Due to the reverse-recovery current of the output diode, using a high-speed diode with a small reverse recovery current is crucial to achieve high efficiency and low EMI. where the internal resistor RM is typically 5.7kΩ; the output current of gain modulator, IMO, is given as a function of input current of IAC pin; and voltages of the VRMS and VEA pins are calculated as: I MO = I AC × 10.5 × (VEA - 0.7) VRMS 2 (VEA MAX - 0.7) (2) Figure 3. Current and Voltage Control Feedback Circuit = I MO ⋅ RM RCS Figure 2. CCM vs. BCM Control Figure 4. Operation Waveforms of CCM PFC Current and Voltage Control of PFC As shown in Figure 3, the FAN6982 employs two control loops for power factor correction: a current-control loop and a voltage-control loop. The current-control loop shapes inductor current, as shown in Figure 4, such that voltage drop across the internal resistor RM should be same as the averaged voltage drop across the sensing resistor, RCS, during one switching cycle: 1 TS TS ∫ (I 0 L ⋅ RCS )dt = I MO ⋅ RM (1) The voltage-control loop regulates PFC output voltage using an internal error amplifier such that the FBPFC voltage is same as the internal reference of 2.5V. Note that, from Equation (2), the voltages of VEA should be almost constant to obtain pure sinusoidal reference for the input current shaping. Because there is always twice the line frequency ripple in the PFC output voltage, a narrow bandwidth should be used for the output voltage-control loop to minimize the line frequency ripple. Otherwise, the control loop tries to remove the output voltage ripple, changing the error amplifier output voltage as shown in Figure 5, which causes distortion of the input current. www.fairchildsemi.com 2 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 AN-6982 APPLICATION NOTE G∝ IAC VBOUT 1 VRMS 2 VEAO BW ⋅G = = 5.8M Ω 159 × 10−6 159 × 10−6 Therefore, 6MΩ resistor is selected for RIAC. www.fairchildsemi.com 7 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 AN-6982 APPLICATION NOTE [STEP-3] PFC Inductor Design The duty cycle of boost switch at the peak of line voltage is given as: DLP = VBOUT − 2VLINE VBOUT (Design Example) The largest ripple factor is obtained at a line voltage as: VLINE = 2VBOUT = 3 2 ⋅ 387 = 182VAC 3 (15) Then the current ripple of the boost inductor at the peak of line voltage is given as: ΔI L = 2VLINE VBOUT − 2VLINE 1 ⋅ ⋅ LBOOST VBOUT f SW With the ripple current specification (50%), the boost inductor is obtained as: LBOOST = 2VBOUT 2 ⋅η 1 2 ⋅ 387 2 ⋅ 0.94 1 ⋅ = ⋅ K RF ⋅ POUT 27 f SW 0.5 ⋅ 350 27 ⋅ 65 × 103 (16) = 916 μ H The average of boost inductor current over one switching cycle at the peak of the line voltage is given as: I L. AVG = 2 POUT VLINE ⋅η The inductor current ripple at low line is obtained as: ΔI L = = 2VLINE VBOUT − 2VLINE 1 ⋅ ⋅ LBOOST VBOUT f SW 2 ⋅ 85 387 − 2 ⋅ 85 1 ⋅ ⋅ = 1.39 A 387 916 × 10−6 65 × 103 (17) The ripple factor (KRF), the ratio between the inductor current ripple and average inductor current at the peak of line voltage load is given as: K RF = ΔI L I L. AVG = The average inductor current at the peak of the line voltage for low line is obtained as: I L. AVG = 2 POUT 2 ⋅ 350 = = 6.19 A VLINE .MIN ⋅η 85 ⋅ 0.94 η ⋅ VLINE 2 VBOUT − 2VLINE 1 ⋅ ⋅ POUT ⋅ LBOOST VBOUT f SW (18) As depicted in Figure 15, the ripple factor has the maximum value when the line voltage is: VLINE .MRF = 2VBOUT 3 ΔI L. AVG The maximum of the inductor current at low line is obtained as: I L PK = I L. AVG + ΔI L / 2 = 6.19 + 1.39 / 2 = 6.89 A (19) [STEP-4] PFC Output Capacitor Selection The output voltage ripple should be considered when selecting the PFC output capacitor. Figure 16 shows the twice line frequency ripple on the output voltage. With a given specification of output ripple, the condition for the output capacitor is obtained as: CBOUT > I BOUT 2π ⋅ f LINE ⋅ VBOUT , RIPPLE IL I L. AVG ΔI L I L. AVG (21) K RF = where IBOUT is nominal output current of boost PFC stage and VBOUT,RIPPLE is the peak-to-peak output voltage ripple specification. The hold-up time also should be considered when determining the output capacitor as: CBOUT > 85VAC 2VBOUT / 3 2 POUT ⋅ tHOLD VBOUT 2 − VBOUT , MIN 2 (22) 264VAC Figure 15. Ripple Factor with Different Line Voltages where POUT is nominal output power of boost PFC stage, tHOLD is the required hold-up time, and VBOUT,MIN is the allowable minimum PFC output voltage during hold-up time. Therefore, with a given current ripple factor (KRF=ΔIL/ILAVG), the boost inductor value is obtained as: LBOOST = 2VBOUT 2 ⋅η 1 ⋅ K RF ⋅ POUT 27 f SW (20) © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 8 AN-6982 APPLICATION NOTE ID V BOUT VREF 3.75 V DD RFB1 FBPFC EN + - SGND + 1.95/2 . 45 + 1.95 /2.45 VEA VRMS I D , AVG I D , AVG = I BOUT (1 − cos(4π ⋅ f LINE ⋅ t )) 20 µA 2.5V - I BOUT VBOUT , RIPPLE = I BOUT 2π f LINE CBOUT RFB2 Figure 17. Block of Range Function VBOUT Figure 16. PFC Output Voltage Ripple The voltage divider network for the PFC output voltage sensing should be designed such that FBPFC voltage is 2.5V at nominal PFC output voltage: VBOUT × RFB 2 = 2.5V RFB1 + RFB 2 (25) (Design Example) With the ripple specification of 12VPP, the capacitor should be: CBOUT I BOUT 0.9 > = = 239 μ F 2π ⋅ f LINE ⋅ VBOUT , RIPPLE 2π ⋅ 50 ⋅12 (Design Example) Assuming the second level of PFC output voltage is 347V: Since minimum allowable output voltage during one cycle line (20ms) drop-outs is 310V, the capacitor should be: CBOUT > 2 PBOUT ⋅ t HOLD VOUT 2 − VOUT , MIN 2 = 2 ⋅ 349 ⋅ 20 × 10−3 387 2 − 3102 = 260 μ F RFB 2 = (1 − = (1 − VBOUT 2 2.5 )⋅ VBOUT 20 ×10 −6 347 2.5 = 12.9k Ω )⋅ 387 20 × 10−6 13kΩ is selected for RFB2. It is checked if the output voltage is higher than the peak of the line voltage: RRMS 1 + RRMS 2 + RRMS 3 π ⋅ ⋅ 2.45 RRMS 3 2 2 × 106 + 200 × 103 + 36 × 103 π ⋅ ⋅ 2.45 36 × 103 2 = 239V < 347V = Then, to obtain 387V for nominal PFC output, Thus, 270μF capacitor is selected for the PFC output capacitor. [STEP-5] PFC Output Sensing Circuit To improve system efficiency at low-line and light-load condition, FAN6982 provides two-level PFC output voltage. As shown in Figure 17, the range function can be enabled or disabled through a resistor connected to ground or VREF. FAN6982 monitors VEA and VRMS voltages to adjust the PFC output voltage and enables a 20µA current source. The PFC output voltage when 20µA is enabled is given as: 20 μA × RFB 2 ) (23) 2.5 It is typical to set the second boost output voltage as 340V~300V. It should be checked if the output voltage is higher than the peak of the line voltage VBOUT 2 = VBOUT × (1 RRMS 1 + RRMS 2 + RRMS 3 π ⋅ ⋅ 2.45 < VBOUT 2 2 RRMS 3 (24) RFB1 = ( =( VBOUT − 1) ⋅ RFB 2 2.5 387 − 1) ⋅ 13 × 103 = 1999k Ω 2.5 2MΩ is selected for RFB1. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 9 AN-6982 APPLICATION NOTE [STEP-6] PFC Current-Sensing Circuit Design Figure 18 shows the PFC compensation circuits for the input current shaping and output voltage regulation. The first step in compensation network design is to select the current-sensing resistor of PFC converter considering the maximum power limit. Since line feed-forward is used, the output power is proportional to the voltage control error amplifier voltage as: VEA − 0.6 (26) VEA SAT − 0.6 SAT where VEA is 5.6V and the maximum power limit of PFC given by the maximum VEA voltage is: POUT (VEA ) = POUT MAX ⋅ POUT MAX = VLINE .BO 2 ⋅ G MAX ⋅ RM RIAC RCS (27) where RM is internal modulator resistor whose typical value is 5.7kΩ, RIAC is a resistor connected between IAC pin, and PFC input and GMAX is the maximum of ratio of IAC pin current and modulator output current (IMO/IAC). The typical value of GMAX is 9 when VRMS pin voltage is 1.05V, which is related to the brownout protection threshold of line voltage (VLINE.BO). It is typical to set the maximum power limit of the PFC stage around 1.2~1.5 of its nominal output power, such that the VEA is around 4~4.5V at nominal output power. By adjusting the current-sensing resistor for the PFC converter, the maximum power limit of the PFC stage can be programmed. To filter out the current ripple of switching frequency, an RC filter is typically used for the ISENSE pin. RLF should not be larger than 100Ω and the time constant of the filter should be 300~500ns to properly remove the leading-edge current spike caused by reverse recovery of output diode. Diodes D1 and D2 are required to prevent over-voltage on the ISENSE pin due to the inrush current that might damage FAN6982. A fast recovery diode or ultra-fast recovery diode is recommended. Figure 18. Gain Modulation Block (Design Example) Setting the maximum power limit of the PFC stage as 450W (around 130% of nominal output power), the current sensing resistor is obtained as: RCS = VLINE . BO 2 ⋅ G MAX ⋅ RM 722 ⋅ 9 ⋅ 5.7 ×103 = = 0.098Ω RIAC PBOUT MAX 6 × 106 ⋅ 450 Thus, 0.1Ω resistor is selected. [STEP-8] PFC Current Loop Design The transfer function from duty cycle to the inductor current of boost power stage is given as: ) iL V ) = BOUT (28) sLBOOST d The transfer function from the output of the current control error amplifier to the inductor current-sensing voltage is obtained as: ) vCS RCS ⋅ VBOUT (29) )= vIEA VRAMP ⋅ sLBOOST where VRAMP is the peak to peak voltage of ramp signal for current control PWM comparator, which is 2.55V. The transfer function of the compensation circuit is given as: s 1+ ) 2π f IC vIEA 2π f II ⋅ )= s vCS s 1+ 2π f IP (30) © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 10 AN-6982 APPLICATION NOTE where: f II = f IP = GMI 1 , f IZ = and 2π ⋅ CIC1 2π ⋅ RIC ⋅ CIC1 1 2π ⋅ RIC ⋅ CIC 2 (31) where GMI is the gain of transconductance error amplifier. The procedure to design the feedback loop is as follows: (a) Determine the crossover frequency (fIC) around 1/10~1/6 of the switching frequency. Then calculate the gain of the transfer function of Equation (29) at crossover frequency as: (Design Example) Setting the crossover frequency as 6kHz (around 1/10 of switching frequency): ) vCS 1 RCS ⋅ VBOUT = ) vIEA @ f = f VRAMP ⋅ 2π f IC ⋅ LBOOST IC = RIC = 0.1 ⋅ 387 = 0.44 2.55 ⋅ 2π ⋅ 6 ×103 ⋅ 916 × 10 −6 = @ f = f IC 1 ) v GMI ⋅ )CS vIEA 1 = 26k Ω 88 × 10−6 ⋅ 0.44 ) vCS ) vIEA = @ f = f IC RCS ⋅ VBOUT VRAMP ⋅ 2π f IC ⋅ LBOOST (32) C IC1 = 1 1 = = 3.1nF RIC ⋅ 2π f C / 3 26 × 103 ⋅ 2π ⋅ 6 × 103 / 3 Setting the pole of the compensator at 60kHz, CIC 2 = 1 2π ⋅ f IP ⋅ RIC = 1 = 0.10nF 2π ⋅ 60 × 103 ⋅ 26 × 103 (b) Calculate RIC that makes the closed-loop gain unity at crossover frequency: RIC = 1 ) vCS GMI ⋅ ) vIEA (33) @ f = f IC The actual components are a little changed for the offthe-shelf components as: RIC=27kΩ , CIC1=3.3nF, and CIC2=100pF. (c) Since the control-to-output transfer function of power stage has -20dB/dec slope and -90o phase at the crossover frequency is 0dB, as shown in Figure 19, it is necessary to place the zero of the compensation network (fIZ) around 1/3 of the crossover frequency so that more than 45° phase margin is obtained. Then the capacitor CIC1 is determined as: C IC1 1 = RIC ⋅ 2π fC / 3 (34) [STEP-9] PFC Voltage Loop Design Since FAN6982 employs line feed-forward, the powerstage transfer function becomes independent of the line voltage. Then the low-frequency, small-signal, control-tooutput transfer function is obtained as: ˆ vBOUT I BOUT ⋅ K MAX 1 ≅ ⋅ ˆ 5 vEA sCBOUT (36) where K MAX = POUT MAX / POUT and 5V is the control window of error amplifier (5.6V-0.6V=5V). (d) Place compensator high-frequency pole (fCP) at least a decade higher than fIC to ensure that it does not interfere with the phase margin of the current loop at its crossover frequency. CIC 2 = 1 2π ⋅ f IP ⋅ RIC (35) Proportional and integration (PI) control with highfrequency pole is typically used for compensation. The compensation zero (fVZ) introduces phase boost, while the high-frequency compensation pole (fVP) attenuates the switching ripple, as shown in Figure 20. Figure 19. Current Loop Compensation © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 Figure 20. Voltage Loop Compensation www.fairchildsemi.com 11 AN-6982 APPLICATION NOTE The transfer function of the compensation network is obtained as: s 1+ ˆ vCOMP 2π fVI 2π fVZ = ⋅ (37) s ˆ vOUT s 1+ 2π fVP where: fVI = fVP = GMV 2.5 1 ⋅ , fVZ = VBOUT 2π ⋅ CVC1 2π ⋅ RVC ⋅ CVC1 1 2π ⋅ RVC ⋅ CVC 2 and (b) Place compensator high-frequency pole (fVP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter so noise can be effectively attenuated. Then, the capacitor CVC2 is determined as: CVC 2 = 1 2π ⋅ fVP ⋅ RVC (41) (38) The procedure to design the feedback loop is as follows: (a) Determine the crossover frequency (fVC) around 1/10~1/5 of the line frequency. Since the control-tooutput transfer function of power stage has -20dB/dec slope and -90o phase at the crossover frequency, as shown in Figure 20 as 0dB; it is necessary to place the zero of the compensation network (fVZ) around the crossover frequency so that 45° phase margin is obtained. Then, the capacitor CVC1 is determined as: GMV ⋅ I BOUT ⋅ K MAX 2.5 ⋅ (39) 5 ⋅ C BOUT ⋅ (2π fVC ) 2 VBOUT where GMV is the gain of the transconductance error amplifier for the output voltage regulation. CVC1 = To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: RVC = 1 2π ⋅ fVC ⋅ CVC1 (40) (Design Example) Setting the crossover frequency as 22Hz: CVC1 = = RVC = GMV ⋅ I BOUT ⋅ K MAX 2.5 ⋅ 2 5 ⋅ CBOUT ⋅ (2π fVC ) VBOUT 70 × 10−6 ⋅ 0.9 ⋅1.27 2.5 ⋅ = 20nF 5 ⋅ 270 × 10−6 ⋅ (2π ⋅ 22) 2 387 1 1 = = 362k Ω 2π ⋅ fVC ⋅ CVC1 2π ⋅ 22 ⋅ 20 ×10−9 Setting the pole of the compensator at 120Hz: CVC 2 = 1 1 = = 3.7 nF 2π ⋅ fVP ⋅ RVC 2π ⋅120 ⋅ 362 × 103 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 12 AN-6982 APPLICATION NOTE 1. Design Summary Application PFC Power Supply Output Power 350W Input Voltage 85~264VAC Output Voltage / Output Current 387V/0.9A Features Switch-charge technique of gain modulator provides better PF and lower THD Over-Voltage Protection (OVP), Under-Voltage (UVP), Open-Loop (OLP), and maximum current limit Protections Range function improves system efficiency at low AC line voltage and light load condition Ready pin function provides power-on sequence for the downstream converter Figure 21. Final Schematic of Design Example © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 13 AN-6982 APPLICATION NOTE Appendix A MOSFET and Diode Reference Specification PFC MOSFETs Voltage Rating 500V 600V FQP13N50C, FQPF13N50C, FDPF20N50(T) Part Number FDP18N50, FDPF18N50, FDA18N50, FDP20N50(T), FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCP20N60S, FCPF20N60S, FCA20N60S, FCP20N60, FCPF20N60 Boost Diodes 600V FFP08H60S, FFPF10H60S, FFP08S60S, FPF08S60SN, BYC10600 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 14 AN-6982 APPLICATION NOTE References FAN6982 — CCM Power Factor Correction Controller AN-8027 — FAN480X PFC+PWM Combo Controller Application AN-6004 — 500W Power Factor Corrected (PFC) Design with FAN4810 AN-6032 — FAN4800 Combo Controller Applications AN-42009 — ML4824 Combo Controller Applications ATX 350W Evaluation Board of FAN6982+FSBH0F70A DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 15