CD4014

CD4014BC 8-Stage Static Shift Register October 1987 Revised January 1999 CD4014BC 8-Stage Static Shift Register General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive. When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/ serial control input is in the logical “1” state, data is jammed into each stage of the register synchronously with the positive transition of the clock. All inputs are protected against static discharge with diodes to VDD and VSS. Features s Wide supply voltage range: s High noise immunity: 3.0V to 15V 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s 5V–10V–15V parametric ratings s Symmetrical output characteristics s Maximum input leakage: 1 µA at 15V over full temperature range Ordering Code: Order Number CD4014BCM CD4014BCN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “x” to the ordering code. Connection Diagram Pin Assignments for DIP Truth Table CL Serial (Note 1) Input Parallel/ Serial PI 1 Control 1 1 1 1 0 0 X 0 1 0 1 X X X Q1 (Internal) 0 1 0 1 0 1 Q1 PI n 0 0 1 1 X X X Qn 0 0 1 1 Qn−1 Qn−1 Qn        X X X X 0 1 X X = Don't care case No Change Note 1: Level change Top View © 1999 Fairchild Semiconductor Corporation DS005947.prf www.fairchildsemi.com CD4014BC Logic Diagram www.fairchildsemi.com 2 CD4014BC Absolute Maximum Ratings(Note 2) (Note 3) Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260°C (Note 3) 700 mW 500 mW −0.5V to +18V −0.5 to VDD + 0.5V −65°C to +150°C Recommended Operating Conditions (Note 3) Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3.0V to 15V 0 to VDD −40°C to +85°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 3: VSS = 0V unless otherwise specified. DC Electrical Characteristics Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VOH HIGH Level Output Voltage VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN Input Current Conditions −40°C Min Max 20 40 80 0.05 0.05 0.05 4.95 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 −0.52 −1.3 −3.6 −0.3 0.3 3.5 7.0 11.0 0.44 1.1 3.0 −0.44 −1.1 −3.0 Min +25°C Typ 0.1 0.2 0.3 0 0 0 5 10 15 2 4 6 3 6 9 0.88 2.2 8 −0.88 −2.2 −8 −10−5 10−5 −0.3 0.3 1.5 3.0 4.0 3.5 7.0 Max 20 40 80 0.05 0.05 0.05 +85°C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 Units µA µA µA V V V V V V V V V V V V mA mA mA mA mA mA VDD = 5V, VIN = VDD or VSS VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V |IO| < 1 µA 9.95 14.95 |IO| < 1 µA 11.0 0.36 0.9 2.4 −0.36 −0.90 −2.4 −1.0 1.0 µA µA Note 4: IOL and IOH are tested one output at a time. 3 www.fairchildsemi.com CD4014BC AC Electrical Characteristics TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ Symbol tPHL, tPLH Parameter Propagation Delay Time (Note 5) Conditions Min Typ 200 80 60 100 50 40 2.8 6 8 4 12 16 90 40 25 180 80 50 15 15 15 60 40 30 80 40 30 100 50 40 120 80 60 160 80 60 200 100 80 0 10 15 5 110 7.5 Max 320 160 120 200 100 80 Units ns ns ns ns ns ns MHz MHz MHz ns ns ns µs µs µs ns ns ns ns ns ns ns ns ns ns ns ns pF pF VDD = 5V VDD = 10V VDD = 15V tTHL, tTLH Transition Time VDD = 5V VDD = 10V VDD = 15V fCL Maximum Clock Input Frequency VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 15V Any Input tW Minimum Clock Pulse Width trCL, tfCL Clock Rise and Fall Time (Note 6) tS Minimum Set-Up Time (Note 7) Serial Input tH ≥ 200 ns Parallel Inputs tH ≥ 200 ns Parallel/Serial Control tH ≥ 200 ns tH Minimum Hold Time Parallel/Serial Control Serial In, Parallel In, tS ≥ 400 ns VDD = 10V CI CPD Average Input Capacitance (Note 8) Power Dissipation Capacitance (Note 8) Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the estimated capacitive load. Note 7: Setup times are measured with reference to clock and a fixed hold time (tH) as specified. Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note AN-90. www.fairchildsemi.com 4 CD4014BC Typical Performance Characteristics 5 www.fairchildsemi.com CD4014BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A www.fairchildsemi.com 6 CD4014BC 8-Stage Static Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.